ZHCSEA4C May 2015 – December 2020 ADS54J40
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | JESD PLL MODE | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1-0 | JESD PLL MODE | R/W | 0h | These bits select the JESD PLL multiplication factor and must match the JESD MODE setting. 00 = 20X mode, four lanes per ADC 01 = Not used 10 = 40X mode, two lanes per ADC 11 = Not used Table 8-14 lists a programming summary of the DDC modes and JESD link configuration. |