ZHCSEA4C May 2015 – December 2020 ADS54J40
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | ADCx_CORR_INT_EST[8:6] | ||
W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | 0 | W | 0h | Must write 0 |
2-0 | ADCx_CORR_INT_EST[8:6] | R/W | 0h | Internal estimate for all four interleaving ADC cores of
the dc offset corrector block can be read from these bits. Keep the R/W bit set to 1 when reading from these registers. See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. |