ZHCSEA4C May 2015 – December 2020 ADS54J40
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | FORMAT EN | 0 | 0 | CTRL IL ENGINE MODE | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0 |
5 | FORMAT EN | R/W | 0h | This bit enables control for data format selection using the FORMAT SEL register bit. 0 = Default, output is in twos complement format 1 = Output is in offset binary format after the FORMAT SEL bit is set |
4-3 | 0 | W | oh | Must write 0 |
2 | CTRL IL ENGINE MODE | R/W | 0h | This bit enables control of
interleaving engine mode selection using the IL ENGINE Mode register
field. 0 = Default. IL Engine Mode (IL Engine enabled) 1 = IL Engine Mode is determined from IL ENGINE MODE field setting. |
1-0 | 0 | W | 0h | Must write 0 |