ZHCSEA4C May 2015 – December 2020 ADS54J40
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | PULSE RESET |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0 |
0 | PULSE RESET | R/W | 0h | This bit must be pulsed after power-up or after
configuring registers in the main digital page of the JESD bank. Any
register bits in the main digital page (6800h) take effect only
after this bit is pulsed; see the Start-Up Sequence section for the correct
sequence. 0 = Normal operation 0 → 1 → 0 = This bit is pulsed |