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AM62D-Q1

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40GFLOPS DSP-Audioprozessor für die Automobilindustrie mit Arm® Cortex®-A53, Cortex-R5F und LPDDR4

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AM62D-Q1

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Produktdetails

CPU 64-bit Coprocessors 2 Arm Cortex-R5F Protocols Ethernet, I2S, TDM, TSN Features Multichannel audio serial ports (McASP) Operating system RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure communication, Secure debug, Secure storage TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125
CPU 64-bit Coprocessors 2 Arm Cortex-R5F Protocols Ethernet, I2S, TDM, TSN Features Multichannel audio serial ports (McASP) Operating system RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure communication, Secure debug, Secure storage TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125
FCCSP (ANF) 484 324 mm² 18 x 18

Processor Cores:

  • Up to Quad Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • DSP with Matrix Multiplication Accelerator based on single-core C7x
    • C7x floating point, up to 40GFLOPS, 256-bit Vector DSP at 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 1.25MB of L2 SRAM with SECDED ECC

Memory Subsystem:

  • Up to 2.29MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
    • 1.25MB of L2 SRAM with SECDED ECC in C7xDSP with Matrix Multiplication Accelerator
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733MT/s
    • Max addressable range of 8GBytes

Functional Safety:

  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
  • Safety-related certification
    • ISO 26262 certification by TÜV SÜD planned
  • AEC - Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection
  • One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
    • High Speed External Processor Data Receive Interface over CSI-2 and MIPI D-PHY

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN-FD support (up to 64-data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass Storage device
  • USB (slave) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm FinFET technology
  • 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)

Processor Cores:

  • Up to Quad Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • DSP with Matrix Multiplication Accelerator based on single-core C7x
    • C7x floating point, up to 40GFLOPS, 256-bit Vector DSP at 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 1.25MB of L2 SRAM with SECDED ECC

Memory Subsystem:

  • Up to 2.29MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
    • 1.25MB of L2 SRAM with SECDED ECC in C7xDSP with Matrix Multiplication Accelerator
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733MT/s
    • Max addressable range of 8GBytes

Functional Safety:

  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
  • Safety-related certification
    • ISO 26262 certification by TÜV SÜD planned
  • AEC - Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection
  • One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
    • High Speed External Processor Data Receive Interface over CSI-2 and MIPI D-PHY

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN-FD support (up to 64-data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) Mass Storage device
  • USB (slave) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm FinFET technology
  • 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)

The AM62D processor from the Sitara™ MPU family is targeted for applications needing high-performance Digital Signal Processing. Some of these applications include:

  • Audio: Automotive premium amplifier and professional audio
  • Radar and Radio: Aerospace and Defense
  • Sonar: Marine equipments
  • Ultrasound: Medical equipments
  • Instrumentation: Current, Voltage, other signals: Test and Measurement

Key cores on the device include the Arm® Cortex®-A53 and C7000™ (“C7x”) scalar and vector DSP core from Texas Instruments, a dedicated Matrix Multiplication Accelerator (MMA), along with an isolated MCU island. All protected by industrial and automotive grade safety and security hardware accelerators.

DSP Core Overview: the C7504 core from C7x family provides up to 40GFLOPS of DSP compute. It achieves 4x to 8x or more performance compared to the previous generation C66x DSP core. Some of the key features includes:

  • 256-bit fixed- and floating-point DSP vector core
  • Single-cycle latency to access L2 memory via Streaming Engine
  • Improved control code efficiency
  • True 64-bit machine with 64-bit memory addressing and single-cycle 64-bit base arithmetic operations

Integration Overview: along with C7x DSP core, the AM62D SoC integrates up to Quad Arm® Cortex®-A53 providing additional 16.8KDMIPS compute and HLOS flexibility of Linux or Real-Time Operating System (RTOS). Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A53 and DSP core’s unencumbered for applications. Integrated diagnostics and safety features support operations up to SIL-2 and ASIL-B levels while the integrated security features protect data against modern day attacks. The AM62D device also offers a 3-port Gigabit Ethernet switch with Time-Sensitive Networking (TSN) to enable audio networking features such as, Ethernet Audio Video Bridging (eAVB) and Dante, while peripherals like the McASP, enable multi-channel I2S and TDM Audio inputs and outputs.

The AM62D processor from the Sitara™ MPU family is targeted for applications needing high-performance Digital Signal Processing. Some of these applications include:

  • Audio: Automotive premium amplifier and professional audio
  • Radar and Radio: Aerospace and Defense
  • Sonar: Marine equipments
  • Ultrasound: Medical equipments
  • Instrumentation: Current, Voltage, other signals: Test and Measurement

Key cores on the device include the Arm® Cortex®-A53 and C7000™ (“C7x”) scalar and vector DSP core from Texas Instruments, a dedicated Matrix Multiplication Accelerator (MMA), along with an isolated MCU island. All protected by industrial and automotive grade safety and security hardware accelerators.

DSP Core Overview: the C7504 core from C7x family provides up to 40GFLOPS of DSP compute. It achieves 4x to 8x or more performance compared to the previous generation C66x DSP core. Some of the key features includes:

  • 256-bit fixed- and floating-point DSP vector core
  • Single-cycle latency to access L2 memory via Streaming Engine
  • Improved control code efficiency
  • True 64-bit machine with 64-bit memory addressing and single-cycle 64-bit base arithmetic operations

Integration Overview: along with C7x DSP core, the AM62D SoC integrates up to Quad Arm® Cortex®-A53 providing additional 16.8KDMIPS compute and HLOS flexibility of Linux or Real-Time Operating System (RTOS). Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A53 and DSP core’s unencumbered for applications. Integrated diagnostics and safety features support operations up to SIL-2 and ASIL-B levels while the integrated security features protect data against modern day attacks. The AM62D device also offers a 3-port Gigabit Ethernet switch with Time-Sensitive Networking (TSN) to enable audio networking features such as, Ethernet Audio Video Bridging (eAVB) and Dante, while peripherals like the McASP, enable multi-channel I2S and TDM Audio inputs and outputs.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet AM62Dx Sitara™ Processors datasheet (Rev. A) PDF | HTML 07 Mai 2025
* Errata AM62Dx Sitara™ Processors Silicon Errata, Silicon Revision 1.0 (Rev. A) PDF | HTML 10 Okt 2025
* User guide AM62D Technical Reference Manual (Rev. A) PDF | HTML 06 Feb 2026
Application note Throughput Characterization of OSPI and QSPI Serial NOR/NAND Flash Operations PDF | HTML 17 Feb 2026
Application note xSPI Custom Flash Debug Guide PDF | HTML 01 Dez 2025
Application note AM62x Audio Design Guide PDF | HTML 20 Nov 2025
User guide Hardware Design Considerations for Custom Board Design using AM62A3, AM62A7-Q1, AM62A1-Q1, AM62D-Q1 Processor (Rev. D) PDF | HTML 24 Okt 2025
User guide AM62A3, AM62A7-Q1, AM62A1-Q1, AM62D-Q1 Processor Family Schematic, Design Guidelines and Review Checklist (Rev. C) PDF | HTML 17 Sep 2025
User guide AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Family Schematic, Design Guidelines and Review Checklist (Rev. I) PDF | HTML 17 Sep 2025
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 05 Sep 2025
White paper How Highly Integrated DSPs for Premium Automotive Audio are Redefining the Driving Experience 04 Mär 2025
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 28 Jan 2025
Application note AM62D Power Estimation Tool PDF | HTML 20 Jan 2025
User guide AM62Ax/AM62Dx Escape Routing for PCB Design (Rev. A) PDF | HTML 14 Jan 2025
Technical article Designing an Efficient Automotive Premium Audio System with Highly Integrated Processors PDF | HTML 18 Dez 2024
Application note AM62Ax, AM62Px LPDDR4 Board Design and Layout Guidelines (Rev. B) PDF | HTML 17 Dez 2024
Application note Sitara™AM62Dx Benchmark PDF | HTML 16 Dez 2024

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

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Das AUDIO-AM62D-EVM-Evaluierungsmodul (EVM) ist eine kostengünstige erweiterbare Plattform für Entwickler zum Prototyping und Evaluieren von Mehrkanal-Audioanwendungen über verschiedene Anwendungsfälle. Das Herzstück des AUDIO-AM62D-EVM ist der AM62D-System-on-Chip (SoC) mit einem 256 Bit breiten (...)

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Debug-Tastkopf

LB-3P-TRACE32-ARM — Debug- und Trace-System Lauterbach TRACE32® für Arm®-basierte Mikrocontroller und Prozessoren

Die TRACE32®-Tools von Lauterbach sind eine Suite hochmoderner Hardware- und Softwarekomponenten, mit denen Entwickler alle Arten von Arm®-basierten Mikrocontrollern und Prozessoren analysieren, optimieren und zertifizieren können. Die weltweit anerkannten Debugging- und Trace-Lösungen für (...)

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Software-Entwicklungskit (SDK)

AM62D-AWE-SDK — AudioWeaver Audio SDK for AM62D

AudioWeaver Audio SDK for AM62D
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Anwendungssoftware und Frameworks

AM62D-RESTRICTED-DOCS-SAFETY — AM62D safety content

This folder contains materials for customers who intend to implement functional safety mechanisms into production.
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Erste Schritte

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development tool ecosystem. It is an integrated development environment (IDE) for TI's microcontrollers, processors, wireless connectivity devices and radar sensors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize (...)

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K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
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SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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Betriebssystem (BS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Von: Green Hills Software
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Betriebssystem (BS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
Von: Green Hills Software
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Betriebssystem (BS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS Vorzertifiziertes Sicherheits-RTOS

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Von: WITTENSTEIN High Integrity Systems
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Simulationsmodell

AM62Dx BSDL Model

SPRM876.ZIP (10 KB) - BSDL Model
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AM62Dx IBIS Model

SPRM878.ZIP (3293 KB) - IBIS Model
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AM62Dx IBIS-AMI Model

SPRM877.ZIP (30794 KB) - IBIS-AMI Model
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Berechnungstool

AM62D-PET-CALC — AM62D Power Estimation Tool

AM62D PET provides power consumption estimates based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision.
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