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AM6548

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Quad Arm® Cortex®-A53 und Dual Arm Cortex-R5F Sitara™ -Prozessor mit Gigabit PRU-ICSS, 3D-Grafikkart

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AM6548

AKTIV
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Produktdetails

CPU 4 Arm Cortex-A53 Frequency (MHz) 1100 Coprocessors 2 Arm Cortex-R5F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols EtherCAT, Ethernet, ICSS, Profibus, Profinet, TSN PCIe 2 PCIe Gen 3 Hardware accelerators CPU only Features Networking Operating system Linux, RTOS Security Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
CPU 4 Arm Cortex-A53 Frequency (MHz) 1100 Coprocessors 2 Arm Cortex-R5F Graphics acceleration 1 3D Display type MIPI DPI, OLDI Protocols EtherCAT, Ethernet, ICSS, Profibus, Profinet, TSN PCIe 2 PCIe Gen 3 Hardware accelerators CPU only Features Networking Operating system Linux, RTOS Security Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
FCCSP (ACD) 784 529 mm² (23 mm × 23 mm)

Processor cores:

  • Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm Cortex-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core

    Industrial subsystem:

  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG

    Memory subsystem:

  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR4 memory types up to DDR-1600
    • 32-bit data bus and 7-bit SECDED bus
    • 8 GB of total addressable space
  • General-Purpose Memory Controller (GPMC)

    Functional Safety:

  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware Integrity up to SIL 2
    • Safety-related certification
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm Cortex-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC

    Security:

  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security software

    SoC services:

  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)

    Multimedia:

  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI DPI parallel interface
    • One port OLDI
  • PowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)

    High-speed interfaces:

  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express ( PCIe) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    General connectivity:

  • 6× Inter-Integrated Circuit ( I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins

    Control interfaces:

  • 6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules

    Automotive interfaces:

  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (MCASP) modules

    Media and data storage:

  • 2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfaces

    Simplified power management:

  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients

    Analog/system integration:

  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change

    System-on-Chip (SoC) architecture:

  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

Processor cores:

  • Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm Cortex-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core

    Industrial subsystem:

  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG

    Memory subsystem:

  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR4 memory types up to DDR-1600
    • 32-bit data bus and 7-bit SECDED bus
    • 8 GB of total addressable space
  • General-Purpose Memory Controller (GPMC)

    Functional Safety:

  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware Integrity up to SIL 2
    • Safety-related certification
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm Cortex-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC

    Security:

  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security software

    SoC services:

  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)

    Multimedia:

  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI DPI parallel interface
    • One port OLDI
  • PowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)

    High-speed interfaces:

  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express ( PCIe) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    General connectivity:

  • 6× Inter-Integrated Circuit ( I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins

    Control interfaces:

  • 6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules

    Automotive interfaces:

  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (MCASP) modules

    Media and data storage:

  • 2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfaces

    Simplified power management:

  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients

    Analog/system integration:

  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change

    System-on-Chip (SoC) architecture:

  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

AM654x and AM652x Sitara™ processors are Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.

AM654x and AM652x Sitara™ processors are Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt AM654x, AM652x Sitara™ Processors Silicon Revision 2.1 datasheet (Rev. C) PDF | HTML 15.09.2023
* Benutzerhandbuch AM65x/DRA80xM Processors Technical Reference Manual (Rev. E) 18.12.2019
* Errata AM65x Processors Silicon Revision 2.1/2.0/1.0 (Rev. I) PDF | HTML 04.05.2023
Anwendungshinweis Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 17.10.2025
Benutzerhandbuch TPS65941319-Q1 PMIC User Guide for Sitara AM65 Processors (Rev. A) PDF | HTML 25.06.2025
Whitepaper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26.02.2025
Anwendungshinweis MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14.05.2024
Anwendungshinweis Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15.11.2023
Whitepaper Time Sensitive Networking for Industrial Automation (Rev. C) PDF | HTML 31.07.2023
Anwendungshinweis Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 24.05.2023
Anwendungshinweis High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24.02.2023
Anwendungshinweis Hardware Design Guide for AM65x Devices (Rev. A) PDF | HTML 22.12.2022
Anwendungshinweis PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 11.10.2022
Whitepaper Utilizing Sitara Processors and Microcontrollers for Industry 4.0 Servo Drives (Rev. C) PDF | HTML 06.10.2021
Anwendungshinweis AM65x/DRA80x Schematic Checklist (Rev. A) PDF | HTML 26.07.2021
Whitepaper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 28.07.2020
E-book Ein Techniker-Leitfaden für Industrieroboter-Designs Download English Version 25.03.2020
Anwendungshinweis AM65x/DRA80xM EMIF Tools (Rev. B) 04.03.2020
Anwendungshinweis AM65xx Time Synchronization Architecture PDF | HTML 14.10.2019
Anwendungshinweis Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 13.09.2019
Technischer Artikel Solving synchronization challenges in Industrial Ethernet PDF | HTML 19.07.2019
Anwendungshinweis Enabling Android Automotive on Your TI Development Board PDF | HTML 12.07.2019
Anwendungshinweis AM65x DDR ECC Initialization and Testing 08.03.2019
Anwendungshinweis AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A) 07.03.2019
Whitepaper Virtualization for embedded industrial systems (Rev. B) 07.03.2019
Anwendungshinweis Integrating a WiLink8 Module with the AM65x EVM 29.01.2019
Anwendungshinweis PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 18.01.2019
Anwendungshinweis PRU Read Latencies (Rev. A) 21.12.2018
Anwendungshinweis PRU-ICSS Getting Starting Guide on Linux (Rev. A) PDF | HTML 10.12.2018
Whitepaper Ensuring real-time predictability (Rev. B) 04.12.2018
Anwendungshinweis AM65xx System Performance 30.11.2018
Whitepaper The state of functional safety in Industry 4.0 27.11.2018
Anwendungshinweis PRU-ICSS / PRU_ICSSG Migration Guide PDF | HTML 05.11.2018
Whitepaper Secure Boot on embedded Sitara™ processors (Rev. A) 13.10.2018
Whitepaper Designing industrial controls for Industry 4.0 with Sitara™ AM6x processors 11.10.2018
Benutzerhandbuch AM654x/DRA80xM BGA Escape Routing Stackup PDF | HTML 29.08.2018
Whitepaper Designing Embedded Systems for High Reliability With Sitara AM6x Processors PDF | HTML 28.08.2018

Design und Entwicklung

Lösungen für die Stromversorgung

Verfügbare Lösungen für die Stromversorgung für den AM6548 finden. TI bietet Stromversorgungslösungen für Ein-Chip-Systeme (SoCs), Prozessoren, Mikrocontroller, Sensoren und feldprogrammierbare Gate-Arrays (FPGAs) von TI und von Fremdherstellern an.

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Evaluierungsplatine

TMDSLCD1EVM — 1280 x 800 LCD-Display-Zubehörkit

Das LCD-Display-Zubehörkit (1280 x 800) ist ein Zusatzzubehör für das AM65x-IDK (TMDX654IDKEVM), um Touch- und Anzeigefunktionen zur Evaluierung von HMI, Industrie-PC und anderen Anwendungen mit Anzeige hinzuzufügen. Das LCD-Display-Zubehörkit (1280 x 800) wird mit dem AM65x-EVM (TMDX654GPEVM) (...)

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TMDX654IDKEVM — AM65x-Entwicklungskit für Industrieanwendungen (IDK)

Das industrielle Entwicklungskit (Industrial Development Kit, IDK) AM65x ist eine Entwicklungsplattform zur Evaluierung der Möglichkeiten der Sitara™ AM65x-Prozessoren im Bereich industrieller Kommunikation und Steuerung für Anwendungen in der Fertigungsautomatisierung, Antriebstechnik, Robotik, (...)

Benutzerhandbuch: PDF | HTML
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MISTR-3P-SOM-AM65X — Mistral Solutions AM65x System-on-Module (SOM)

The AM65x SOM from Mistral is an easy to use, compact, light-weight system on module (SOM) providing very high processing power for industrial applications. This module is based on Texas Instruments Sitara™ AM6548 SoC and is ideal for complex processing, connectivity and control required for (...)

Von: Mistral Solutions Pvt. Ltd
Unterstützte Produkte und Hardware
Evaluierungsplatine

TQ-3P-SITARASOMS — Sitara-SOMs der TQ-Gruppe

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
Von: TQ-Group
Unterstützte Produkte und Hardware
Evaluierungsplatine

TQ-3P-SOM-TQMA65XX — TQ-Group TQMa65xx System auf Modul für AM6528 Arm-basierten Prozessor

Das Embedded-Modul TQMa65xx, basierend auf der ARM® Cortex®-A53 Technologie von Texas Instruments. Der integrierte Grafikcontroller unterstützt Anwendungen mit Display und Touch. Vier Prozessorvarianten stehen für verschiedene Anwendungen wie Netzwerktechnik, industrielle Automatisierung (...)

Von: TQ-Group
Unterstützte Produkte und Hardware
Evaluierungsplatine

ZLG-3P-M65XX — Systemmodul ZLG M65xx für Prozessor AM65xx Arm Cortex-A53, 1,1 GHz

Für die Hauptplatine der Serie M65xx werden Komponenten der Baureihe AM65xx von TI mit einem Dual-Core-/Quad-Core-Cortex®-Prozessor A53 mit einer Hauptfrequenz von bis zu 1,1 GHz und zwei Cortex-Kernen mit einer Hauptfrequenz von 400 MHz®-R5F-Kernel, auf Wunsch mit DDR3L-Speicher mit 1 oder 2 (...)

Von: Guangzhou ZHIYUAN Electronics Co.,Ltd.
Unterstützte Produkte und Hardware
Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

Unterstützte Produkte und Hardware
Vorrätig
Limit:
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Nicht verfügbar
Software-Entwicklungskit (SDK)

MCU-PLUS-SDK-AM65X — MCU+ SDK for AM65x – RTOS

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit. Alle Versionen des Prozessor-SDK lassen sich (...)

Unterstützte Produkte und Hardware
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-AM65X — Linux processor SDK for AM65x

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit. Alle Versionen des Prozessor-SDK lassen sich (...)

Unterstützte Produkte und Hardware
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-RT-AM65X — Linux-RT processor SDK for AM65x

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit. Alle Versionen des Prozessor-SDK lassen sich (...)

Unterstützte Produkte und Hardware
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-AM65X — RTOS Prozessor-SDK für AM65x (Keine Designunterstützung von TI verfügbar. Einzelheiten finden Sie unter Übersicht - RTOS-Highlights)

Das Prozessor-SDK (Software Development Kit) ist eine vereinheitliche Softwareplattform für alle Embedded-Prozessoren von TI. Es ist einfach einzurichten und bringt bereits alle Funktionen für den schnellen Zugriff auf Benchmarks und Demos mit. Alle Versionen des Prozessor-SDK lassen sich (...)

Unterstützte Produkte und Hardware
IDE, Konfiguration, Compiler oder Debugger

C2000_CLA_SAFETI_CQKIT_RV — C2000™ and CLA safety compiler qualification kit (leverages compiler release validations)

Das Sicherheits-Compiler-Qualifizierungskit möchte Kunden dabei unterstützen, den Einsatz des ARM C/C++-Compilers C6000, C7000 oder C2000/CLA von TI für funktionale Sicherheitsstandards wie beispielsweise IEC 61508 und ISO 26262 zu qualifizieren.

Das Sicherheits-Compiler-Qualifizierungskit:

  • ist für (...)
Unterstützte Produkte und Hardware
IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

Unterstützte Produkte und Hardware
IDE, Konfiguration, Compiler oder Debugger

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

Unterstützte Produkte und Hardware
Betriebssystem (BS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Unterstützte Produkte und Hardware
Betriebssystem (BS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)

Von: Green Hills Software
Unterstützte Produkte und Hardware
Treiber oder Bibliothek

PRU-ICSS-ETHERCAT-SLAVE — PRU-ICSS software for EtherCAT slave

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)

Unterstützte Produkte und Hardware
Treiber oder Bibliothek

PRU-ICSS-HSR-PRP-DAN — PRU-ICSS software for HSR/PRP

Das PRU-ICSS-Protokoll ermöglicht industrielle Echtzeitkommunikation für TI Sitara-Prozessoren.  Die PRU-ICSS-Protokolle basieren auf Prozessor-SDK-RTOS, der einheitlichen Softwareentwicklungsplattform von TI. Sie enthalten optimierte PRU-ICSS-Firmware, einen entsprechenden PRU-ICSS-Treiber für den (...)

Unterstützte Produkte und Hardware
Treiber oder Bibliothek

WIND-3P-VXWORKS-LINUX-OS — Wind-River-Prozessoren VxWorks und Linux-Betriebssysteme

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)

Von: Wind River Systems
Unterstützte Produkte und Hardware
Software-Programmiertool

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash ist Teil des umfassenden CCStudio™-Entwicklungsökosystem von TI und ein Softwaretool zur Programmierung des integrierten Flash-Speichers von TI-Mikrocontrollern und drahtlosen Kommunikationsbausteinen sowie des integrierten Flash-Speichers für TI-Prozessoren. UniFlash bietet sowohl (...)

Unterstützte Produkte und Hardware
Simulationsmodell

AM654x/DRA80xM BSDL Model

SPRM724.ZIP (12 KB) - BSDL-Modell
Unterstützte Produkte und Hardware
Simulationsmodell

AM654x/DRA80xM IBIS File

SPRM737.ZIP (19753 KB) - IBIS-Modell
Unterstützte Produkte und Hardware
Simulationsmodell

AM654x/DRA80xM Thermal Models

SPRM718.ZIP (2 KB) - Wärmemodell
Unterstützte Produkte und Hardware
Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
Unterstützte Produkte und Hardware
Berechnungstool

SITARA-DDR-CONFIG-TOOL — Sitara External Memory Interface (EMIF)-Tool

Das Sitara™ EMIF-Tool ist ein Softwaretool, das eine Schnittstelle zur Konfiguration der TI-Prozessoren für den Zugriff auf die externen DDR-Speicherbausteine bereitstellt. Das Tool optimiert auch die Delay Locked Loop (DLL)-Einstellungen, um Versatz beim Platinenlayout zu kompensieren. Die (...)

Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCCSP (ACD) 784 Ultra Librarian
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