ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a programmable LVDS mapping mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 53 | X | MAP_CH34_TO_OUT3B[3:0] | |||||
R/W-0 | R/W-0 | R/W-0 | |||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | |||||||
R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 53 | R/W | 0 | Enable register 53h(1) This bit enables register 53h. |
D14-D12 | X | R/W | 0 | Don't care bits |
D11-D8 | MAP_CH34_TO_OUT3B[3:0] | R/W | 0 | OUT3B pin to channel mapping These bits select the OUT3B pin pair to channel data mapping. |
D7-D0 | X | R/W | 0 | Don't care bits |