ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a test pattern register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | EN_FRAME_PAT | ADCLKOUT[11:0] | |||||
R/W-0 | R/W-0 | R/W-0 | |||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
ADCLKOUT[11:0] | X | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | X | R/W | 0 | Don't care bit |
D14 | EN_FRAME_PAT | R/W | 0 | Frame pattern enable 0 = Normal frame clock operation 1 = Enables the output frame clock to be programmed through a pattern |
D13-D2 | ADCLKOUT[11:0] | R/W | 0 | ADCLK pin frame clock pattern These bits determine the 12-bit pattern for the frame clock on the ADCLKP and ADCLKN pins. |
D1-D0 | X | R/W | 0 | Don't care bits |