ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is an output interface mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
ENABLE 46 | X | FALL_SDR | X | EN_16BIT | EN_14BIT | EN_12BIT | X |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | EN_SDR | MSB_FIRST | BTC_MODE | X | EN_2LANE | ||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | ENABLE 46 | R/W | 0 | Enable register 46(1) This bit enables register 46. |
D14 | X | R/W | 0 | Don't care bit |
D13 | FALL_SDR | R/W | 0 | SDR output mode 0 = At data window edge 1 = The LCLK rising or falling edge control comes in the middle of the data window when operating in SDR output mode |
D12 | X | R/W | 0 | Don't care bit |
D11 | EN_16BIT | R/W | 0 | 16-bit mode enable 0 = Inactive 1 = 16-bit serialization mode enabled; ensure bits D[10:9] are 0 |
D10 | EN_14BIT | R/W | 0 | 14-bit mode enable 0 = Inactive 1 = 14-bit serialization mode enabled; ensure bits D11 and D9 are 0 |
D9 | EN_12BIT | R/W | 0 | 12-bit mode enable 0 = Inactive 1 = 12-bit serialization mode enabled; ensure bits D[11:10] are 0 |
D8-D5 | X | R/W | 0 | Don't care bits |
D4 | EN_SDR | R/W | 0 | Bit clock selection 0 = DDR bit clock 1 = SDR bit clock |
D3 | MSB_FIRST | R/W | 0 | MSB first selection 0 = LSB first 1 = MSB first |
D2 | BTC_MODE | R/W | 0 | Binary mode selection 0 = Binary offset (ADC data output format) 1 = Binary twos complement (ADC data output format) |
D1 | X | R/W | 0 | Don't care bit |
D0 | EN_2LANE | R/W | 0 | LVDS output lane selection 0 = One-lane LVDS output 1 = Two-lane LVDS output |