ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
The analog input consists of a switched-capacitor-based differential sample-and-hold architecture, as shown in Figure 42. This differential topology results in very good AC performance even for high-input frequencies at high sampling rates. The INx_P and INx_M pins must be externally biased around a common-mode voltage of 0.95 V, available on the VCM pin. For a full-scale differential input, each input pin (INx_P, INx_M) must swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The input sampling circuit has a high 3-dB bandwidth that extends up to 550 MHz (measured from the input pins to the sampled voltage).