ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a test pattern register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | PAT_SYNC | PAT_DESKEW | |||||
R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D2 | X | R/W | 0 | Don't care bits |
D1 | PAT_SYNC | R/W | 0 | Sync pattern enable 0 = Inactive 1 = Sync pattern mode enabled; ensure that D0 is 0 |
D0 | PAT_DESKEW | R/W | 0 | Deskew pattern enable 0 = Inactive 1 = Deskew pattern mode enabled; ensure that D1 is 0 |