ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
The VSP5324-Q1 output interface is normally a DDR interface with the LCLK rising and falling edge transitions in the middle of alternate data windows. Figure 46 shows this default phase.
The LCLK phase can be programmed relative to the output frame clock and data using the PHASE_DDR[1:0] bits in Table 4. Figure 47 shows the LCLK phase modes.
ADDRESS (HEX) | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
42 | EN_REF_VCM0 | X(1) | X | X | X | X | X | X | X | PHASE_DDR[1:0] | X | EN_REF_VCM1 | X | X | X |