ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
The VSP5324-Q1 device offers several flexible output options which makes interfacing to an (application-specific integrated circuit) ASIC or an (field-programmable gate array) FPGA easy. Each option can be easily programmed using the serial interface. Table 3 lists a summary of all options. This table also lists the default values after power-up and reset and a detailed description of each option. The output interface options are one-lane and two-lane serialization, and are described in the One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock and Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock sections, respectively.
FEATURE | OPTIONS | AVAILABLE IN | DEFAULT AFTER RESET | DESCRIPTION | |
---|---|---|---|---|---|
ONE-LANE | TWO-LANE | ||||
Lane interface | One and two lanes | Yes | Yes | One-lane | One-lane: ADC data are sent serially over one pair of LVDS pins Two-lane: ADC data are split and sent serially over two pairs of LVDS pins |
Serialization factor | 12x | Yes | No | 12x | — |
DDR bit clock frequency | 6x | Yes | No | 6x | — |
3x | No | Yes | — | Only with two-lane interface | |
Frame clock frequency | 1x sample rate | Yes | No | 1x | — |
1/2x sample rate | No | Yes | — | Only with two-lane interface | |
Bit sequence | Byte-wise | No | Yes | Byte-wise | These options are available only with two-lane interface. Byte wise: ADC data are split into upper and lower bytes that are output on separate lanes. Bit wise: ADC data are split into even and odd bits that are output on separate lanes. Word wise: Successive ADC data samples are sent over separate lanes. |
Bit-wise | No | Yes | Byte-wise | ||
Word-wise | No | Yes | Byte-wise |