ZHCSH90A January   2015  – December 2017 VSP5324-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化的原理图
      2.      信噪比与输入信号频率间的关系
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Dynamic Performance
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Electrical Characteristics: Digital
    8. 6.8  Timing Requirements
    9. 6.9  LVDS Timing at Different Sampling Frequencies (One-Lane Interface, 12x Serialization)
    10. 6.10 LVDS Timing at Different Sampling Frequencies (Two-Lane Interface, 6x Serialization)
    11. 6.11 Serial Interface Timing Requirements
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Large- and Small-Signal Input Bandwidth
      2. 7.3.2 Digital Processing Block
        1. 7.3.2.1 Digital Gain
        2. 7.3.2.2 ADC Input Polarity Inversion
        3. 7.3.2.3 SYNC Function
        4. 7.3.2.4 Output Data Format
      3. 7.3.3 Serial LVDS Interface
        1. 7.3.3.1 One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock
        2. 7.3.3.2 Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock
      4. 7.3.4 Bit Clock Programmability
      5. 7.3.5 LVDS Output Data and Clock Buffers
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Reference Mode Of Operation
        1. 7.4.1.1 Using the REF Pins
        2. 7.4.1.2 Using the VCM Pin
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
      3. 7.5.3 Serial Register Readout
    6. 7.6 Register Maps
      1. 7.6.1 Serial Registers
        1. 7.6.1.1  Register 00h (offset = 00h) [reset = 0]
          1. Table 7. Register 00h Field Descriptions
        2. 7.6.1.2  Register 01h (offset = 01h) [reset = 0]
          1. Table 8. Register 01h Field Descriptions
        3. 7.6.1.3  Register 02h (offset = 02h) [reset = 0]
          1. Table 9. Register 02h Field Descriptions
        4. 7.6.1.4  Register 0Ah (offset = 0Ah) [reset = 0]
          1. Table 10. Register 0Ah Field Descriptions
        5. 7.6.1.5  Register 0Fh (offset = 0Fh) [reset = 0]
          1. Table 11. Register 0Fh Field Descriptions
        6. 7.6.1.6  Register 14h (offset = 14h) [reset = 0]
          1. Table 12. Register 14h Field Descriptions
        7. 7.6.1.7  Register 1Ch (offset = 1Ch) [reset = 0]
          1. Table 13. Register 1Ch Field Descriptions
        8. 7.6.1.8  Register 23h (offset = 23h) [reset = 0]
          1. Table 14. Register 23h Field Descriptions
        9. 7.6.1.9  Register 24h (offset = 24h) [reset = 0]
          1. Table 15. Register 24h Field Descriptions
        10. 7.6.1.10 Register 25h (offset = 25h) [reset = 0]
          1. Table 16. Register 25h Field Descriptions
        11. 7.6.1.11 Register 26h (offset = 26h) [reset = 0]
          1. Table 17. Register 26h Field Descriptions
        12. 7.6.1.12 Register 27h (offset = 27h) [reset = 0]
          1. Table 18. Register 27h Field Descriptions
        13. 7.6.1.13 Register 28h (offset = 28h) [reset = 0]
          1. Table 19. Register 28h Field Descriptions
        14. 7.6.1.14 Register 29h (offset = 29h) [reset = 0]
          1. Table 20. Register 29h Field Descriptions
        15. 7.6.1.15 Register 2Ah (offset = 2Ah) [reset = 0]
          1. Table 21. Register 2Ah Field Descriptions
        16. 7.6.1.16 Register 2Bh (offset = 2Bh) [reset = 0]
          1. Table 22. Register 2Bh Field Descriptions
        17. 7.6.1.17 Register 2Eh (offset = 2Eh) [reset = 0]
          1. Table 23. Register 2Eh Field Descriptions
        18. 7.6.1.18 Register 30h (offset = 30h) [reset = 0]
          1. Table 24. Register 30h Field Descriptions
        19. 7.6.1.19 Register 33h (offset = 33h) [reset = 0]
          1. Table 25. Register 33h Field Descriptions
        20. 7.6.1.20 Register 35h (offset = 35h) [reset = 0]
          1. Table 26. Register 35h Field Descriptions
        21. 7.6.1.21 Register 38h (offset = 38h) [reset = 0x0000]
          1. Table 27. Register 38h Field Descriptions
        22. 7.6.1.22 Register 42h (offset = 42h) [reset = 0]
          1. Table 28. Register 42h Field Descriptions
        23. 7.6.1.23 Register 45h (offset = 45h) [reset = 0]
          1. Table 29. Register 45h Field Descriptions
        24. 7.6.1.24 Register 46h (offset = 46h) [reset = 0]
          1. Table 30. Register 46h Field Descriptions
        25. 7.6.1.25 Register 50h (offset = 50h) [reset = 0]
          1. Table 31. Register 50h Field Descriptions
        26. 7.6.1.26 Register 51h (offset = 51h) [reset = 0]
          1. Table 32. Register 51h Field Descriptions
        27. 7.6.1.27 Register 53h (offset = 53h) [reset = 0]
          1. Table 33. Register 53h Field Descriptions
        28. 7.6.1.28 Register 54h (offset = ) [reset = 0]
          1. Table 34. Register 54h Field Descriptions
        29. 7.6.1.29 Register 55h (offset = 55h) [reset = 0]
          1. Table 35. Register 55h Field Descriptions
        30. 7.6.1.30 Register F0h (offset = F0h) [reset = 0]
          1. Table 36. Register F0h Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Drive Circuit Requirements
        2. 8.2.2.2 Clock Input
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines
      2. 10.1.2 Grounding
      3. 10.1.3 Supply Decoupling
      4. 10.1.4 Exposed Pad
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.3 Serial LVDS Interface

The VSP5324-Q1 device offers several flexible output options which makes interfacing to an (application-specific integrated circuit) ASIC or an (field-programmable gate array) FPGA easy. Each option can be easily programmed using the serial interface. Table 3 lists a summary of all options. This table also lists the default values after power-up and reset and a detailed description of each option. The output interface options are one-lane and two-lane serialization, and are described in the One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock and Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock sections, respectively.

Table 3. Summary of Output Interface Options

FEATURE OPTIONS AVAILABLE IN DEFAULT AFTER RESET DESCRIPTION
ONE-LANETWO-LANE
Lane interface One and two lanes Yes Yes One-lane One-lane: ADC data are sent serially over one pair of LVDS pins
Two-lane: ADC data are split and sent serially over two pairs of LVDS pins
Serialization factor 12x Yes No 12x —
DDR bit clock frequency 6x Yes No 6x —
3x No Yes — Only with two-lane interface
Frame clock frequency 1x sample rate Yes No 1x —
1/2x sample rate No Yes — Only with two-lane interface
Bit sequence Byte-wise No Yes Byte-wise These options are available only with two-lane interface.
Byte wise: ADC data are split into upper and lower bytes that are output on separate lanes.
Bit wise: ADC data are split into even and odd bits that are output on separate lanes.
Word wise: Successive ADC data samples are sent over separate lanes.
Bit-wise No Yes Byte-wise
Word-wise No Yes Byte-wise