ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
In the two-lane serialization option, the 12-bit ADC data are serialized and output over two LVDS pairs per channel. The output data rate is a 6x sample rate with a 3x bit clock and a 1x frame clock.
Compared to the one-line scenario, the two-line output data rate is half the amount. This difference allows the device to be used up to the maximum sampling rate. Two-lane serialization is available in bit-, byte-, and word-wise modes. Figure 44 shows the bit- and byte-wise modes and Figure 45 shows the word-wise mode.
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The upper number is the data bit in MSB-first mode. The lower number in parenthesis is the data bit in LSB-first mode.NOINDENT:
The unshaded cells indicate sample N data. The shaded cells indicate sample N + 1 data.NOINDENT:
The upper number is the data bit in MSB-first mode. The lower number in parenthesis is the data bit in LSB-first mode.NOINDENT:
The unshaded cells indicate sample N data. The shaded cells indicate sample N + 1 data.