ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a power-down mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | PDN_PIN_CFG | PDN_ COMPLETE | PDN_PARTIAL | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
PDN_CH4 | X | PDN_CH3 | X | PDN_CH2 | X | PDN_CH1 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D11 | X | R/W | 0 | Don't care bits |
D10 | PDN_PIN_CFG | R/W | 0 | PD pin configuration 0 = PD pin configured for complete power-down mode 1 = PD pin configured for partial power-down mode |
D9 | PDN_ COMPLETE | R/W | 0 | Complete power-down 0 = Normal operation 1 = Register mode for complete power-down (slower recovery) |
D8 | PDN_PARTIAL | R/W | 0 | Partial power-down 0 = Normal operation 1 = Partial power-down mode (fast recovery from power-down) |
D7 | PDN_CH4 | R/W | 0 | ADC power-down mode for channel 4 0 = Normal operation 1 = Partial power-down mode (fast recovery from power-down) |
D6 | X | R/W | 0 | Don't care bit |
D5 | PDN_CH3 | R/W | 0 | ADC power-down mode for channel 3 0 = Normal operation 1 = ADC power-down mode for channel 3 |
D4-D3 | X | R/W | 0 | Don't care bits |
D2 | PDN_CH2 | R/W | 0 | ADC power-down mode for channel 2 0 = Normal operation 1 = ADC power-down mode for channel 2 |
D1 | X | R/W | 0 | Don't care bit |
D0 | PDN_CH1 | R/W | 0 | ADC power-down mode for channel 1 0 = Normal operation 1 = ADC power-down mode for channel 1 |