ZHCSH90A January   2015  – December 2017 VSP5324-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化的原理图
      2.      信噪比与输入信号频率间的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Dynamic Performance
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Electrical Characteristics: Digital
    8. 6.8  Timing Requirements
    9. 6.9  LVDS Timing at Different Sampling Frequencies (One-Lane Interface, 12x Serialization)
    10. 6.10 LVDS Timing at Different Sampling Frequencies (Two-Lane Interface, 6x Serialization)
    11. 6.11 Serial Interface Timing Requirements
    12. 6.12 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Large- and Small-Signal Input Bandwidth
      2. 7.3.2 Digital Processing Block
        1. 7.3.2.1 Digital Gain
        2. 7.3.2.2 ADC Input Polarity Inversion
        3. 7.3.2.3 SYNC Function
        4. 7.3.2.4 Output Data Format
      3. 7.3.3 Serial LVDS Interface
        1. 7.3.3.1 One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock
        2. 7.3.3.2 Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock
      4. 7.3.4 Bit Clock Programmability
      5. 7.3.5 LVDS Output Data and Clock Buffers
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Reference Mode Of Operation
        1. 7.4.1.1 Using the REF Pins
        2. 7.4.1.2 Using the VCM Pin
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
      3. 7.5.3 Serial Register Readout
    6. 7.6 Register Maps
      1. 7.6.1 Serial Registers
        1. 7.6.1.1  Register 00h (offset = 00h) [reset = 0]
          1. Table 7. Register 00h Field Descriptions
        2. 7.6.1.2  Register 01h (offset = 01h) [reset = 0]
          1. Table 8. Register 01h Field Descriptions
        3. 7.6.1.3  Register 02h (offset = 02h) [reset = 0]
          1. Table 9. Register 02h Field Descriptions
        4. 7.6.1.4  Register 0Ah (offset = 0Ah) [reset = 0]
          1. Table 10. Register 0Ah Field Descriptions
        5. 7.6.1.5  Register 0Fh (offset = 0Fh) [reset = 0]
          1. Table 11. Register 0Fh Field Descriptions
        6. 7.6.1.6  Register 14h (offset = 14h) [reset = 0]
          1. Table 12. Register 14h Field Descriptions
        7. 7.6.1.7  Register 1Ch (offset = 1Ch) [reset = 0]
          1. Table 13. Register 1Ch Field Descriptions
        8. 7.6.1.8  Register 23h (offset = 23h) [reset = 0]
          1. Table 14. Register 23h Field Descriptions
        9. 7.6.1.9  Register 24h (offset = 24h) [reset = 0]
          1. Table 15. Register 24h Field Descriptions
        10. 7.6.1.10 Register 25h (offset = 25h) [reset = 0]
          1. Table 16. Register 25h Field Descriptions
        11. 7.6.1.11 Register 26h (offset = 26h) [reset = 0]
          1. Table 17. Register 26h Field Descriptions
        12. 7.6.1.12 Register 27h (offset = 27h) [reset = 0]
          1. Table 18. Register 27h Field Descriptions
        13. 7.6.1.13 Register 28h (offset = 28h) [reset = 0]
          1. Table 19. Register 28h Field Descriptions
        14. 7.6.1.14 Register 29h (offset = 29h) [reset = 0]
          1. Table 20. Register 29h Field Descriptions
        15. 7.6.1.15 Register 2Ah (offset = 2Ah) [reset = 0]
          1. Table 21. Register 2Ah Field Descriptions
        16. 7.6.1.16 Register 2Bh (offset = 2Bh) [reset = 0]
          1. Table 22. Register 2Bh Field Descriptions
        17. 7.6.1.17 Register 2Eh (offset = 2Eh) [reset = 0]
          1. Table 23. Register 2Eh Field Descriptions
        18. 7.6.1.18 Register 30h (offset = 30h) [reset = 0]
          1. Table 24. Register 30h Field Descriptions
        19. 7.6.1.19 Register 33h (offset = 33h) [reset = 0]
          1. Table 25. Register 33h Field Descriptions
        20. 7.6.1.20 Register 35h (offset = 35h) [reset = 0]
          1. Table 26. Register 35h Field Descriptions
        21. 7.6.1.21 Register 38h (offset = 38h) [reset = 0x0000]
          1. Table 27. Register 38h Field Descriptions
        22. 7.6.1.22 Register 42h (offset = 42h) [reset = 0]
          1. Table 28. Register 42h Field Descriptions
        23. 7.6.1.23 Register 45h (offset = 45h) [reset = 0]
          1. Table 29. Register 45h Field Descriptions
        24. 7.6.1.24 Register 46h (offset = 46h) [reset = 0]
          1. Table 30. Register 46h Field Descriptions
        25. 7.6.1.25 Register 50h (offset = 50h) [reset = 0]
          1. Table 31. Register 50h Field Descriptions
        26. 7.6.1.26 Register 51h (offset = 51h) [reset = 0]
          1. Table 32. Register 51h Field Descriptions
        27. 7.6.1.27 Register 53h (offset = 53h) [reset = 0]
          1. Table 33. Register 53h Field Descriptions
        28. 7.6.1.28 Register 54h (offset = ) [reset = 0]
          1. Table 34. Register 54h Field Descriptions
        29. 7.6.1.29 Register 55h (offset = 55h) [reset = 0]
          1. Table 35. Register 55h Field Descriptions
        30. 7.6.1.30 Register F0h (offset = F0h) [reset = 0]
          1. Table 36. Register F0h Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Drive Circuit Requirements
        2. 8.2.2.2 Clock Input
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines
      2. 10.1.2 Grounding
      3. 10.1.3 Supply Decoupling
      4. 10.1.4 Exposed Pad
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Typical Characteristics

Typical values are at 25°C, V(AVDD) = 1.8 V, V(LVDD) = 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and –1-dBFS differential analog input, unless otherwise noted.
VSP5324-Q1 D001_sles275.gif
SNR = 69.6 dBFS SINAD = 69.5 dBFS
SFDR = 89.3 dBc THD = 85.9 dBc
Sample Rate = 80 MSPS
Figure 4. FFT for 5-MHz Input Signal
VSP5324-Q1 D003_sles275.gif
SNR = 68.5 dBFS SINAD = 67.8 dBFS
SFDR = 76.5 dBc THD = 75 dBc
Sample Rate = 80 MSPS
Figure 6. FFT for 65-MHz Input Signal
VSP5324-Q1 D002_sles275.gif
SNR = 69.6 dBFS SINAD = 69.4 dBFS
SFDR = 84.8 dBc THD = 83.2 dBc
Sample Rate = 80 MSPS
Figure 5. FFT for 15-MHz Input Signal
VSP5324-Q1 D004_sles275.gif
SNR = 69.8 dBFS SINAD = 69.7 dBFS
SFDR = 85.1 dBc THD = 84.7 dBc
Sample Rate = 40 MSPS
Figure 7. FFT For 5-MHz Input Signal
VSP5324-Q1 D005_sles275.gif
SNR = 69.6 dBFS SINAD = 69.5 dBFS
SFDR = 86.8 dBc THD = 84 dBc
Sample Rate = 40 MSPS
Figure 8. FFT for 15-MHz Input Signal
VSP5324-Q1 D007_sles275.gif
Figure 10. Signal-to-Noise Ratio (SNR) vs Input Signal Frequency
VSP5324-Q1 D009_sles275.gif
Figure 12. SNR vs Digital Gain
VSP5324-Q1 D011_sles275.gif
ƒIN = 5 MHz
Figure 14. Performance vs Input Signal Amplitude
VSP5324-Q1 D013_sles275.gif
ƒIN = 5 MHz
Figure 16. Performance vs Input Clock Duty Cycle
VSP5324-Q1 D015_sles275.gif
ƒIN = 5 MHz External reference using the VCM pin
Figure 18. Performance in External Reference Mode
VSP5324-Q1 D017_sles275.gif
ƒIN = 5 MHz
Figure 20. SFDR vs AVDD and Temperature
VSP5324-Q1 D019_sles275.gif
ƒIN = 5 MHz
Figure 22. SFDR vs DVDD and Temperature
VSP5324-Q1 D021_sles275.gif
A 0.7-VPP 5-MHz sine-wave input is applied on the INx_P pin
The INx_M pin is connected to the device VCM pin
Figure 24. SFDR vs Temperature for Single-ended Input
VSP5324-Q1 D023_sles275.gif
Figure 26. Differential Nonlinearity
VSP5324-Q1 D025_sles275.gifFigure 28. Filter Response (Decimate-by-2)
VSP5324-Q1 D027_sles275.gif
Figure 30. Digital High-Pass Filter Response
VSP5324-Q1 D029_sles275.gif
Figure 32. FFT With HPF Enabled and Disabled
(No Input Signal)
VSP5324-Q1 D031_sles275.gifFigure 34. FFT (0 MHz to 1 MHz) for 5-MHz Input Signal
(Sample Rate = 80 MSPS With Low-Frequency Noise Suppression Enabled)
VSP5324-Q1 D033_sles275.gifFigure 36. Analog Supply Current
VSP5324-Q1 D035_sles275.gifFigure 38. Digital Supply Current
VSP5324-Q1 D006_sles275.gif
SNR = 67.2 dBFS SINAD = 66.6 dBFS
SFDR = 76.5 dBc THD = 74 dBc
Sample Rate = 40 MSPS
Figure 9. FFT for 65-MHz Input Signal
VSP5324-Q1 D008_sles275.gif
Figure 11. Spurious-Free-Dynamic Range (SFDR) vs Input Signal Frequency
VSP5324-Q1 D010_sles275.gif
Figure 13. SFDR vs Digital Gain
VSP5324-Q1 D012_sles275.gif
ƒIN = 5 MHz
Figure 15. Performance vs Input Clock Amplitude
VSP5324-Q1 D014_sles275.gif
ƒIN = 5 MHz
Figure 17. Performance vs Input Common-Mode
VSP5324-Q1 D016_sles275.gif
ƒIN = 5 MHz
Figure 19. SNR vs AVDD and Temperature
VSP5324-Q1 D018_sles275.gif
ƒIN = 5 MHz
Figure 21. SNR vs DVDD and Temperature
VSP5324-Q1 D020_sles275.gif
A 0.7-VPP 5-MHz sine-wave input is applied on the INx_P pin
The INx_M pin is connected to the device VCM pin
Figure 23. SNR vs Temperature For Single-Ended Input
VSP5324-Q1 D022_sles275.gif
Figure 25. Integral Nonlinearity
VSP5324-Q1 D024_sles275.gif
ƒIN = 3 MHz 50-mVPP signal superimposed on the input common-mode
Figure 27. CMRR vs Frequency
VSP5324-Q1 D026_sles275.gifFigure 29. Filter Response (Decimate-by-4)
VSP5324-Q1 D028_sles275.gif
SNR = 70.8 dBFS SINAD = 70.7 dBFS SFDR = 88.7 dBc
THD = 87.3 dBc Decimate-by-2 filter enabled
Figure 31. FFT for 5-MHz Input Signal
(Sample Rate = 80 MSPS With Decimation Filter = 2)
VSP5324-Q1 D030_sles275.gif
SNR = 70.8 dBFS SINAD = 70.7 dBFS
SFDR = 88.7 dBc THD = 87.3 dBc
Figure 33. FFT (Full-Band) for 5-MHz Input Signal
(Sample Rate = 80 MSPS With Low-Frequency Noise Suppression Enabled)
VSP5324-Q1 D032_sles275.gifFigure 35. FFT (39 MHz to 40 MHz) for 5-MHz Input Signal
(Sample Rate = 80 MSPS With Low-Frequency Noise Suppression Enabled)
VSP5324-Q1 D034_sles275.gifFigure 37. Power Consumption on Analog Supply
VSP5324-Q1 D036_sles275.gifFigure 39. Power Consumption on Digital Supply