7.5.3 Serial Register Readout
The device includes a mode where the contents of the internal registers can be readback on the SDOUT pin, as shown in Figure 49. This mode can useful as a diagnostic check to verify the serial interface communication between the external controller and ADC.
By default, after power-up and device reset, the SDOUT pin is high-impedance. When readout mode is enabled using the READOUT register bit, the SDOUT pin outputs the contents of the selected register serially in the following sequence:
- The READOUT register bit must be set to 1 in order for the device to enter readout mode. This setting disables any further writes into the internal registers, except for the register at address 01h. Note that the READOUT bit is also located in this register. The device can exit readout mode by writing the READOUT bit to 0. Only the register contents of address 01h are unable to be read in register readout mode.
- The read cycle is initiated by clocking the register address A[7:0] on the SDIN pin.
- The device serially outputs the contents (D[15:0]) of the selected register on the SDOUT pin.
- The external controller latches the contents at the SCLK rising edge.
- The READOUT register bit is set to 0 to exit serial readout mode, which enables all registers of the device to be written to. At this point, the SDOUT pin enters a high-impedance state.
After reset, the device default states include the following:
- The device is in normal operation mode with 12x serialization enabled for all channels.
- Output interface is one-lane, 12x serialization with a 6x bit clock and a 1x frame clock frequency.
- Data format is LSB-first and offset binary.
- Serial readout is disabled.
- The PD pin is configured as a global power-down pin.
- Digital gain is set to 0 dB.