ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
The 12-bit ADC data are serialized and output over one LVDS pair per channel along with a 6x bit clock and 1x frame clock, as shown in Figure 43. The output data rate is 12x sample rate and is therefore suited for low sample rates (typically up to 50 MSPS).
NOINDENT:
Upper number is the data bit in MSB-first mode. Lower number in parenthesis is the data bit in LSB-first mode.