ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a digital gain mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | GAIN_CH3[3:0] | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | GAIN_CH4[3:0] | ||||||
R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D12 | X | R/W | 0 | Don't care bits |
D11-D8 | GAIN_CH3[3:0] | R/W | 0 | Channel 3 gain These bits set the programmable gain of channel 3 |
D7-D4 | X | R/W | 0 | Don't care bits |
D3-D0 | GAIN_CH4[3:0] | R/W | 0 | Channel 4 gain These bits set the programmable gain of channel 4 |