ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a test pattern register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
PRBS_SEED[22:16] | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
INVERT_CH4 | X | INVERT_CH3 | X | INVERT_CH2 | X | INVERT_CH1 | |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D9 | PRBS_SEED[22:16] | R/W | 0 | PRBS pattern seed value, upper bits These bits determine the PRBS pattern starting seed value of the upper seven bits. |
D8 | X | R/W | 0 | Don't care bit |
D7 | INVERT_CH4 | R/W | 0 | Analog input pin polarity for channel 4 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 4 |
D6 | X | R/W | 0 | Don't care bit |
D5 | INVERT_CH3 | R/W | 0 | Analog input pin polarity for channel 3 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 3 |
D4-D3 | X | R/W | 0 | Don't care bits |
D2 | INVERT_CH2 | R/W | 0 | Analog input pin polarity for channel 2 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 2 |
D1 | X | R/W | 0 | Don't care bit |
D0 | INVERT_CH1 | R/W | 0 | Analog input pin polarity for channel 1 0 = Normal configuration (default) 1 = Electrically swaps the analog input pin polarity for channel 1 |