ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a digital filter mode register. All bits default to 0 after reset.
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
| X | HPF_EN_CH3 | HPF_CORNER _CH3[3:0] | FILTER3_COEFF_SET[2:0] | ||||
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | ||||
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| FILTER3_COEFF_SET[2:0] | FILTER3_RATE[2:0] | X | ODD_TAP3 | USE_FILTER3 | |||
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| D15 | X | R/W | 0 | Don't care bit |
| D14 | HPF_EN_CH3 | R/W | 0 | Channel 3 HPF filter enable 0 = Disabled 1 = HPF filter enable for channel 3 |
| D13-D10 | HPF_CORNER _CH3[3:0] | R/W | 0 | HPF corner for channel 3 These bits set the HPF corner in values from 2k to 10k. |
| D9-D7 | FILTER3_COEFF_SET[2:0] | R/W | 0 | Filter 3 coefficient set These bits select the stored coefficient set for filter 3. |
| D6-D4 | FILTER3_RATE[2:0] | R/W | 0 | Filter 3 decimation factor These bits set the decimation factor for filter 3. |
| D3 | X | R/W | 0 | Don't care bit |
| D2 | ODD_TAP3 | R/W | 0 | Filter 3 odd tap This bit uses odd tap filter 3. |
| D1 | X | R/W | 0 | Don't care bit |
| D0 | USE_FILTER3 | R/W | 0 | Channel 3 filter 0 = Disabled 1 = Enables filter for channel 3 |