ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DIGITAL INx_PUTS (RESET, SCLK, SDATA, CS, PDN, SYNC, INT/EXT) | |||||||
VIH | High-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | > 1.3 | V | |||
VIL | Low-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | < 0.4 | V | |||
IIH | High-level input current | VIH = 1.8 V | 6 | µA | |||
IIL | Low-level input current | VIL = 0 V | < 0.1 | µA | |||
DIGITAL OUTPUTS | |||||||
VOH | High-level output voltage | CMOS interface (SDOUT) | AVDD – 0.1 | V | |||
VOL | Low-level output voltage | CMOS interface (SDOUT) | 0.1 | V | |||
VOD(H) | High-level output differential voltage | LVDS interface (OUTP, OUTM, LCLKP, LCLKM, ADCLKP, ADCLKM), with an external 100-Ω termination | 245 | 420 | mV | ||
VOD(L) | Low-level output differential voltage | LVDS interface (OUTP, OUTM, LCLKP, LCLKM, ADCLKP, ADCLKM), with an external 100-Ω termination | –420 | –245 | mV | ||
VOC | Output common-mode voltage | 1.05 | V |