ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
The VSP5324-Q1 device is a high-performance, 12-bit, quad-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. The conversion process is initiated by a rising edge of the external input clock and when the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 11 clock cycles. The output is available as 12-bit data, in serial (low-voltage differential signaling) LVDS format, coded in either offset binary or binary twos complement format.