ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
The VSP5324-Q1 device has a set of internal registers that can be accessed by the serial interface formed by the CS (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. When CS is low the following occurs:
If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active CS pulse.
The first eight bits form the register address and the remaining 16 bits form the register data. The interface can function with SCLK frequencies from 15 MHz down to very low speeds (of few Hertz) and also with a non-50% SCLK duty cycle.