ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is an output interface mode register.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
EN_REF_VCM0 | X | ||||||
R/W-0 | R/W-0 | ||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | PHASE_DDR[1:0] | X | EN_REF_VCM1 | X | |||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15 | EN_REF_VCM0 | R/W | 0 | To enable the external reference mode, the EN_EXT_REF register bit (register F0h) must be set to 1. 00 = In external reference mode, apply the reference on the REFT, REFB pins 01, 10 = Don't use 11 = In external reference mode, apply the reference on the VCM pin |
D14-D7 | X | R/W | 0 | Don't care bits |
D6-D5 | PHASE_DDR[1:0] | R/W | 0 | These bits control the LCLK output phase relative to data. (Default = 10) |
D4 | X | R/W | 0 | Don't care bit |
D3 | EN_REF_VCM1 | R/W | 0 | To enable the external reference mode, the EN_EXT_REF register bit (register F0h) must be set to 1. 00 = In external reference mode, apply the reference on the REFT, REFB pins 01, 10 = Don't use 11 = In external reference mode, apply the reference on the VCM pin |
D2-D0 | X | R/W | 0 | Don't care bits |