ZHCSH90A January 2015 – December 2017 VSP5324-Q1
PRODUCTION DATA.
This is a digital filter mode register. All bits default to 0 after reset.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 |
X | |||||||
R/W-0 | |||||||
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
X | GLOBAL_EN_FILTER | X | |||||
R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15-D2 | X | R/W | 0 | Don't care bits |
D1 | GLOBAL_EN_FILTER | R/W | 0 | Filter block enable 0 = Inactive 1 = Global control filter blocks enabled |
D0 | X | R/W | 0 | Don't care bit |