ZHCSN24 数据表 | 德州仪器 TI.com.cn

ZHCSN24A August 2019 – May 2021 TPS53676

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6.4.19 PMBus/AVS Interfaces

VCC = 3.3 V, CSPIN = VIN_CSNIN = 12 V, T_J = -40 to 125 ℃ unless otherwise specified

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
PMBus Timing and Physical Characteristics
t_PMB-BUF	PMBus Free time between STOP and START conditions ⁽¹⁾		0.5			µs
t_PMB-HD-STA	Hold time after Repeated Start Condition ⁽¹⁾		0.26			µs
t_PMB-SU-STO	Stop condition Setup time ⁽¹⁾		0.26			µs
t_PMB-HD-DAT	SMB_DIO Hold Time ⁽¹⁾ ⁽²⁾		0			µs
t_PMB-SU-DAT	SMB_DIO Setup Time		50			ns
t_PMB-TIMEOUT	SMB_CLK low timeout ⁽¹⁾ ⁽³⁾		25		35	ms
t_PMB-LOW	SMB_CLK low time ⁽¹⁾		0.5			µs
t_PMB-HIGH	SMB_CLK high time ⁽¹⁾ ⁽⁴⁾		0.26		50	µs
t_PMB-LOW-SEXT	Maximum clock stretching time (slave) ⁽¹⁾ ⁽⁵⁾				25	ms
t_PMB-LOW-MEXT	Maximum clock stretching time (master) ⁽¹⁾ ⁽⁶⁾				10	ms
t_R-PMB	SMB_DIO/SMB_CLK rise time, ( V_IL(MAX)-150 mV to V_IH(MIN)+150 mV) ⁽¹⁾	100 kHz Class			1000	ns
		400 kHz Class			300	ns
		1000 kHz Class			120	ns
t_F-PMB	SMB_DIO/SMB_CLK fall time, ( V_IH(MIN)+150 mV to V_IL(MAX) + 150 mV) ⁽¹⁾	100 kHz Class			1000	ns
		400 kHz Class			300	ns
		1000 kHz Class			120	ns
t_PMB-REJ	Noise spike suppression-time ⁽¹⁾ ⁽⁷⁾				50	ns
I_LK-PMB-BUS	Input leakage per PMBus segment ⁽¹⁾		-200		200	µA
I_LK-PMB-PIN	Input leakage for PMBus pins		-10		10	µA
C_PMB-BUS	PMBus Bus Capacitance ⁽¹⁾				400	pF
C_PMB-PIN	PMBus Pin Capacitance ⁽¹⁾				10	pF
V_{PULLUP_PMBus}	PMBus interface pull ups ⁽¹⁾		1.62		3.63	V
V_{IL_PMBus}	SMB_DIO, SMB_CLK Input logic low				0.8	V
V_{IH_PMBus}	SMB_DIO, SMB_CLK Input logic high		1.35			V
V_{HYST_PMBus}	Hysteresis voltage		80			mV
V_{OL_PMBus}	Low-level output voltage	I_OL = -20 mA			0.4	V
PMB_CLKR	PMBus clock frequency range ⁽¹⁾	PMBus Clock Requirements ⁽⁹⁾	0.05		2	MHz
AVSBus Timing and Physical Characteristics
t_P-AVS	AVS_CLK Active Clock Period ⁽¹⁾		20		200	ns
t_HIGH-AVSCLK	AVS_CLK high period ⁽¹⁾		10			ns
t_LOW-AVSCLK	AVS_CLK low period ⁽¹⁾			t_P-AVS/2		ns
t_TO-AVSCLK	AVS Clock Timeout Delay ⁽¹⁾	Clock idle period before clock timeout condition is recognized		5		µs
N_PRECLK-AVS	Number of preamble AVSCLK required to accept AVS frame after AVS clock timeout ⁽¹⁾		2			cycles
t_R-AVSDAT	AVS_MDATA, AVS_SDATA rise time ⁽¹⁾				3	ns
t_F-AVSDAT	AVS_MDATA, AVS_SDATA fall time ⁽¹⁾				3	ns
t_PD-AVS	Time for signals to propagate from one device to another ⁽¹⁾				4	ns
t_CAPT-AVSS	Time from falling clock edge in Master to data capture inside slave ⁽¹⁾		t_PD-AVS	2+t_PD-AVS		ns
t_SU-AVSS	Time from data-out edge in Master to clock edge in Slave ⁽¹⁾		2+t_PD-AVS			ns
t_LAUNCH-AVSS	Time from rising clock edge in Master to data-out transition at Slave's data-out port ⁽¹⁾ ⁽⁸⁾		2+t_PD-AVS	8 + t_PD-AVS	14 + t_PD-AVS	ns
t_H-AVSM	Time from capture clock edge in Master to data-out edge in Slave (for next bit) ⁽¹⁾		2	t_LOW-AVSCLK		ns
I_LK-AVS	AVSBus pin (AVS_MDATA, AVS_SDATA, AVS_CLK, AVS_VDDIO) leakage		-10		10	µA
V_DDIO-AVSBus	AVS_VDDIO input range		1.14		3.6	V
V_IL-AVSMDA	AVS_MDATA input logic low				0.4*V_DDIO	V
V_IH-AVSMDA	AVS_MDATA input logic high		0.6*V_DDIO			V
V_OL-AVSSDA	AVS_SDATA output logic low				0.2*V_DDIO	V
V_OH-AVSSDA	AVS_SDATA output logic high		0.8*V_DDIO			V
AVS_CLKR	AVSBus clock frequency range ⁽¹⁾	AVSBus Clock Requirements	5		50 ⁽¹⁰⁾	MHz

(1) Specified by Design.

(2) A device must internally provide sufficient hold time for the SMBDAT signal (with respect to the V_{IH, MIN} of the SMBCLK signal) to bridge the undefined region of the falling edge of SMBCLK.

(3) Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of t_{TIMEOUT, MIN}. After the master in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than t_{TIMEOUT, MAX}. Typical device examples include the host controller, and embedded controller, and most devices that can master the SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or a stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds the SMBCLK low for t_{TIMEOUT, MAX} or longer

(4) t_{PMB-HIGH, MAX} provides a simple guaranteed method for masters to detect bus idle conditions. A master can assume that the bus is free if it detects that the clock and data signals have been high for greater than t_{HIGH, MAX}.

(5) t_PMB-LOW-SEXT is the cumulative time a given slave device is allowed to extend the clock cycles in one message from the initial START to the STOP. It is possible that another slave device or the master also extends the clock, causing the combined clock low extend time to be greater than tLOW:SEXT. Therefore, this parameter is measured with the slave device as the sole target of a full-speed master

(6) t_PMB-LOW-MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device or another master also extends the clock, causing the combined clock low time to be greater

(7) Devices must provide a means to reject noise spikes of a duration up to the maximum specified value.

(8) The clock used by the slave is a delayed version of the clock in the master. For that reason, launching data from the slave starts later than launching from the master, and relatively speaking, capturing by the master comes earlier. If tdelay is large on a given board, it may be necessary to increase thigh to compensate and give more time for the data to go from the slave to the master.

(9) I2C High-speed mode is not supproted.

(10) Due to the upper limit t_LAUNCH-AVSSoperation at 50 MHz typically requires changing the duty cycle of the AVS_CLK to allow more launch time for the TPS53676

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6.4.19 PMBus/AVS Interfaces