ZHCSN24A August 2019 – May 2021 TPS53676
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Logic Interface Pins | ||||||
| VAENL | Channel A ENABLE Logic Low | 0.975 | V | |||
| VAENH | Channel A ENABLE Logic High | 1.525 | V | |||
| VAENHYS | Channel A ENABLE Hysteresis (1) | 0.4 | 0.6 | V | ||
| tAENDIG | Channel A ENABLE Deglitch (1) | 0.275 | µs | |||
| tAENVRRDYF | Channel A ENABLE Low to VRRDY Low | No soft-stop; Only valid when using AVR_EN pin. | 1.5 | µs | ||
| IAENH | Channel A I/O Leakage | Leakage current , VAVR_EN = 1.1 V | 25 | µA | ||
| VBENL | Channel B ENABLE Logic Low | 0.925 | V | |||
| VBENH | Channel B ENABLE Logic High | 1.225 | V | |||
| VBENHYS | Channel B ENABLE Hysteresis (1) | 0.2 | 0.3 | V | ||
| tBENDIG | Channel B ENABLE Deglitch (1) | 0.275 | µs | |||
| tBENVRRDYF | Channel B ENABLE Low to VRRDY Low (1) | No soft-stop; Only valid when using BVR_EN pin. | 1.5 | µs | ||
| IBENH | Channel B I/O Leakage | Leakage current , VBVR_EN = 1.1 V | 25 | µA | ||
| VPWML | PWMx Output Low-level | ILOAD = ± 0.5 mA | 0.11 | V | ||
| VPWMH | PWMx Output High-level | ILOAD = ± 0.5 mA; VCC = 2.97 V | 2.85 | V | ||
| VPWM_Tri | PWMx Tri-State | ILOAD = ± 100 µA | 1.440 | 1.5 | 1.560 | V |
| tP-S_H-L | PWMx H-L Transition-time (1) | CLOAD = 10 pF; ILOAD = ± 100 µA; 10% to 90% both edges | 10 | ns | ||
| tP-S_TRI | PWMx Tri-State Transition (1) | CLOAD = 10 pF; ILOAD = ± 100 µA; 10% or 90% to tri-state; both edges | 20 | ns | ||