제품 상세 정보

Sample rate (max) (Msps) 80, 200 Resolution (Bits) 10, 12 Number of input channels 4, 8 Interface type Serial LVDS Analog input BW (MHz) 500 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 560 Architecture Pipeline SNR (dB) 70.3 ENOB (Bits) 11.3 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 80, 200 Resolution (Bits) 10, 12 Number of input channels 4, 8 Interface type Serial LVDS Analog input BW (MHz) 500 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 560 Architecture Pipeline SNR (dB) 70.3 ENOB (Bits) 11.3 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Configurable Modes of Operation:
    • 10-Bit, 200-MSPS, 4-Channel ADC
    • 12-Bit, 160-MSPS, 4-Channel ADC
    • 10-Bit, 100-MSPS, 8-Channel ADC
    • 12-Bit, 80-MSPS, 8-Channel ADC
  • Designed for Low Power:
    • 65 mW per Channel at 80 MSPS
      (12-Bit, 8-Channel)
    • 150 mW per Channel at 200 MSPS
      (10-Bit, 4-Channel)
  • 12-Bit, 80 MSPS:
    • SNR: 70.3 dBFS
  • 10-Bit, 200 MSPS:
    • SNR: 61.3 dBFS
    • Interleaving Spur: > 60 dBc at 90 MHz
  • Serial LVDS One-Wire Interface:
    • 10x Serialization up to 1000 Mbps Data Rate per Wire
    • 12x Serialization up to 960 Mbps Data Rate per Wire
  • Digital Processing Block:
    • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
    • Programmable IIR High-Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
  • Low-Frequency Noise Suppression Mode
  • Programmable Mapping Between ADC Input Channels and LVDS Output Pins
  • Channel Averaging Mode
  • Variety of LVDS Test Patterns to Verify
    Data Capture by FPGA or Receiver
  • Package: 9-mm × 9-mm QFN-64
  • Configurable Modes of Operation:
    • 10-Bit, 200-MSPS, 4-Channel ADC
    • 12-Bit, 160-MSPS, 4-Channel ADC
    • 10-Bit, 100-MSPS, 8-Channel ADC
    • 12-Bit, 80-MSPS, 8-Channel ADC
  • Designed for Low Power:
    • 65 mW per Channel at 80 MSPS
      (12-Bit, 8-Channel)
    • 150 mW per Channel at 200 MSPS
      (10-Bit, 4-Channel)
  • 12-Bit, 80 MSPS:
    • SNR: 70.3 dBFS
  • 10-Bit, 200 MSPS:
    • SNR: 61.3 dBFS
    • Interleaving Spur: > 60 dBc at 90 MHz
  • Serial LVDS One-Wire Interface:
    • 10x Serialization up to 1000 Mbps Data Rate per Wire
    • 12x Serialization up to 960 Mbps Data Rate per Wire
  • Digital Processing Block:
    • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
    • Programmable IIR High-Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
  • Low-Frequency Noise Suppression Mode
  • Programmable Mapping Between ADC Input Channels and LVDS Output Pins
  • Channel Averaging Mode
  • Variety of LVDS Test Patterns to Verify
    Data Capture by FPGA or Receiver
  • Package: 9-mm × 9-mm QFN-64

The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. However, the device can also be configured to operate as a 4-channel ADC running at 2x the sample rate by interleaving data from two ADC channels. In interleaving mode, the device accepts a double frequency input clock. Each ADC in a pair converts a common analog input signal at alternate rising edges of the 2x input clock. The device can either be configured as a 10-bit, 4-channel ADC with sample rates up to 200 MSPS or as a 12-bit, 4-channel ADC with sample rates up to 160 MSPS.

The data from each ADC within the interleaved pair is output in serial format over one LVDS pair up to a maximum data rate of 1 Gbps (10 bits at 100 MSPS). With interleaving disabled, the ADS5296A can also be operated as an 8-channel, 10-bit device with sample rates up to 100 MSPS.

Several digital functions commonly used in systems are included in the device. These functions include a low-frequency noise suppression (LFNS) mode, digital filtering options, and programmable mapping of LVDS output pins and analog input channels.

For low input frequency applications, the LFNS mode enables the suppression of noise at low frequencies and improves SNR in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters as well as dc offset removal filters.

Low power consumption and integration of multiple channels in a small package makes the device attractive for high channel count data acquisition systems. The device is available in a compact 9-mm × 9-mm QFN-64 package. The ADS5296A is specified over the –40°C to +85°C operating temperature range.

The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. However, the device can also be configured to operate as a 4-channel ADC running at 2x the sample rate by interleaving data from two ADC channels. In interleaving mode, the device accepts a double frequency input clock. Each ADC in a pair converts a common analog input signal at alternate rising edges of the 2x input clock. The device can either be configured as a 10-bit, 4-channel ADC with sample rates up to 200 MSPS or as a 12-bit, 4-channel ADC with sample rates up to 160 MSPS.

The data from each ADC within the interleaved pair is output in serial format over one LVDS pair up to a maximum data rate of 1 Gbps (10 bits at 100 MSPS). With interleaving disabled, the ADS5296A can also be operated as an 8-channel, 10-bit device with sample rates up to 100 MSPS.

Several digital functions commonly used in systems are included in the device. These functions include a low-frequency noise suppression (LFNS) mode, digital filtering options, and programmable mapping of LVDS output pins and analog input channels.

For low input frequency applications, the LFNS mode enables the suppression of noise at low frequencies and improves SNR in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters as well as dc offset removal filters.

Low power consumption and integration of multiple channels in a small package makes the device attractive for high channel count data acquisition systems. The device is available in a compact 9-mm × 9-mm QFN-64 package. The ADS5296A is specified over the –40°C to +85°C operating temperature range.

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* Data sheet 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel ADC . datasheet 2013/10/30

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 모듈(EVM)용 GUI

SLAC547 ADS5295 and ADS5296 GUI Installer, v2.1

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

시뮬레이션 모델

ADS5296 IBIS Model

SBAM169.ZIP (13 KB) - IBIS Model
계산 툴

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 착수하기 (...)
패키지 CAD 기호, 풋프린트 및 3D 모델
VQFN (RGC) 64 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

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