ADS1601
- High Speed:
- Data Rate: 1.25MSPS
- Bandwidth: 615kHz
- Outstanding Performance:
- SNR: 92dB at fIN = 100kHz, –1dBFS
- THD: –103dB at fIN = 100kHz, –6dBFS
- SFDR: 105dB at fIN = 100kHz, –6dBFS
- Ease-of-Use:
- High-Speed 3-Wire Serial Interface
- Directly Connects to TMS320 DSPs
- On-Chip Digital Filter Simplifies Anti-Alias Requirements
- Simple Pin-Driven Control—No On-Chip Registers to Program
- Selectable On-Chip Voltage Reference
- Simultaneous Sampling with Multiple ADS1601s
- Low Power:
- 330mW at 1.25MSPS
- 145mW at 625kSPS
- Power-Down Mode
The ADS1601 is a high-speed, high-precision, delta-sigma analog-to-digital converter (ADC) manufactured on an advanced CMOS process. The ADS1601 oversampling topology reduces clock jitter sensitivity during the sampling of high-frequency, large amplitude signals by a factor of four over that achieved by Nyquist-rate ADCs. Consequently, signal-to-noise ratio (SNR) is particularly improved. Total harmonic distortion (THD) is –103dB, and the spurious-free dynamic range (SFDR) is 105dB
Optimized for power and performance, the ADS1601 dissipates only 330mW while providing a full-scale differential input range of ±0.94VREF. Having such a wide input range makes out-of-range signals uncommon. The OTR pin indicates if an analog input out-of-range condition does occur. The differential input signal is measured against the differential reference, which can be generated internally on the ADS1601 or supplied externally.
The ADS1601 uses an inherently stable advanced modulator with an on-chip decimation filter. The filter stop band extends to 19.3MHz, which greatly simplifies the anti-aliasing circuitry. The modulator samples the input signal up to 20MSPS, depending on fCLK, while the 16x decimation filter uses a series of four half-band FIR filter stages to provide 75dB of stop band attenuation and 0.001dB of passband ripple.
Output data is provided over a simple 3-wire serial interface at rates up to 1.25MSPS, with a –3dB bandwidth of 615kHz. The output data or its complementary format directly connects to DSPs such as TI’s TMS320 family, FPGAs, or ASICs. A dedicated synchronization pin enables simultaneous sampling with multiple ADS1601s in multi-channel systems. Power dissipation is set by an external resistor that allows a reduction in dissipation when operating at slower speeds. All of the ADS1601 features are controlled by dedicated I/O pins, which simplify operation by eliminating the need for on-chip registers.
The high performing, easy-to-use ADS1601 is especially suitable for demanding measurement applications in sonar, vibration analysis, and data acquisition. The ADS1601 is offered in a small, 7mm × 7mm TQFP-48 package and is specified from –40°C to +85°C.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | 16-Bit, 1.25MSPS Analog-to-Digital Converter datasheet (Rev. D) | 2011. 10. 20 | ||
| 애플리케이션 노트 | Digital Filter Types in Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2023. 3. 29 | ||
| 애플리케이션 노트 | ADS16xx Reference Options (Rev. A) | PDF | HTML | 2022. 3. 9 | ||
| e북 | Fundamentals of Precision ADC Noise Analysis (Rev. A) | 2020. 6. 19 | |||
| 백서 | Voltage-reference impact on total harmonic distortion | 2016. 8. 1 | |||
| e북 | Best of Baker's Best: Precision Data Converters -- Delta-Sigma ADCs | 2015. 3. 19 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
아날로그 엔지니어의 계산기는 아날로그 회로 설계 엔지니어가 정기적으로 사용하는 많은 반복 계산의 속도를 높이도록 설계되었습니다. 이 PC 기반 툴은 피드백 저항을 사용한 연산 증폭기 게인 설정부터 아날로그-디지털 컨버터(ADC) 드라이브 버퍼 회로 안정화를 위한 적절한 회로 설계 요소 선택에 이르기까지 다양한 일반적인 계산 목록이 포함된 그래픽 인터페이스를 제공합니다.
이 계산기는 독립 실행형 툴로 유용할 뿐만 아니라 아날로그 엔지니어의 포켓 레퍼런스에 설명된 개념과도 잘 어울립니다.
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.