The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS,
analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data
rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide
frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog
inputs up to very high input frequencies. A sampling clock divider allows more flexibility for
system clock architecture design.
The devices employ internal dither algorithms to provide excellent spurious-free
dynamic range (SFDR) over a large input frequency range.
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 날짜 |
|---|---|---|---|---|
| * | Data sheet | ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters datasheet (Rev. F) | PDF | HTML | 2014/12/22 |
| Application note | Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai | 2016/05/02 | ||
| User guide | TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) | PDF | HTML | 2016/01/11 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/05/22 | ||
| White paper | Ready to make the jump to JESD204B? White Paper (Rev. B) | 2015/03/19 | ||
| User guide | Interoperability of TI ADS42JB69 Family of JESD204B ADCs with Altera FPGAs | 2013/10/04 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/07/19 | ||
| Application note | LMK04828 as a Clock Source for the ADS42JB69 | 2012/11/14 |
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
The ADS42JB49EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42JB49 and LMK04828 clock jitter cleaner. The ADS42JB49 is a low power, 14-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.
Calculator installer
General calculator tool for analog design support.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.