ADS5413

활성

12비트, 65MSPS, 1.0GHz 입력 대역폭 아날로그-디지털 컨버터(ADC)

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document-pdfAcrobat ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter datasheet (영어)

ADS5413

활성

데이터 시트

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제품 상세 정보

Sample rate (max) (Msps)

65

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS

Analog input BW (MHz)

1000

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2.25

Power consumption (typ) (mW)

400

Architecture

Pipeline

SNR (dB)

68.5

ENOB (Bits)

11.3

SFDR (dB)

81

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

65

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS

Analog input BW (MHz)

1000

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2.25

Power consumption (typ) (mW)

400

Architecture

Pipeline

SNR (dB)

68.5

ENOB (Bits)

11.3

SFDR (dB)

81

Operating temperature range (°C)

-40 to 85

Input buffer

No

HTQFP (PHP)

48

81 mm² (9 mm × 9 mm)

12-Bit Resolution
65-MSPS Maximum Sample Rate
2-Vpp Differential Input Range
3.3-V Single Supply Operation
1.8-V to 3.3-V Output Supply
400-mW Total Power Dissipation
Two’s Complement Output Format
On-Chip S/H and Duty Cycle Adjust Circuit
Internal or External Reference
48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size)
64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
Power-Down Mode
Single-Ended or Differential Clock
1-GHz -3-dB Input Bandwidth
APPLICATIONS
- High IF Sampling Receivers
- Medical Imaging
- Portable Instrumentation

CommsADC is a trademark of Texas Instruments.

12-Bit Resolution
65-MSPS Maximum Sample Rate
2-Vpp Differential Input Range
3.3-V Single Supply Operation
1.8-V to 3.3-V Output Supply
400-mW Total Power Dissipation
Two’s Complement Output Format
On-Chip S/H and Duty Cycle Adjust Circuit
Internal or External Reference
48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size)
64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
Power-Down Mode
Single-Ended or Differential Clock
1-GHz -3-dB Input Bandwidth
APPLICATIONS
- High IF Sampling Receivers
- Medical Imaging
- Portable Instrumentation

CommsADC is a trademark of Texas Instruments.

The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.

The device is specified over full temperature range (–40°C to +85°C).

The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.

The device is specified over full temperature range (–40°C to +85°C).

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10개 모두 보기

상위 문서	유형	직함	날짜
*	데이터 시트	ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter datasheet	2003. 12. 16
	애플리케이션 노트	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	2015. 5. 22
	애플리케이션 노트	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	2013. 7. 19
	애플리케이션 노트	High-Speed, Analog-to-Digital Converter Basics	2012. 1. 11
	애플리케이션 노트	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	2010. 9. 10
	애플리케이션 노트	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	2009. 4. 28
	애플리케이션 노트	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	2008. 6. 8
	애플리케이션 노트	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2008. 6. 2
	애플리케이션 노트	Standard Procedure Direct Measurement Sub-picosecond RMS Jitter High-Speed ADC	2004. 6. 30
	애플리케이션 노트	How to Calculate the Period Jitter from the SSCR for High-Speed ADCs	2003. 12. 17

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ADC-HARMONIC-CALC — ADC Frequency Calculator Download

The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

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ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

아날로그 엔지니어의 계산기는 아날로그 회로 설계 엔지니어가 정기적으로 사용하는 많은 반복 계산의 속도를 높이도록 설계되었습니다. 이 PC 기반 툴은 피드백 저항을 사용한 연산 증폭기 게인 설정부터 아날로그-디지털 컨버터(ADC) 드라이브 버퍼 회로 안정화를 위한 적절한 회로 설계 요소 선택에 이르기까지 다양한 일반적인 계산 목록이 포함된 그래픽 인터페이스를 제공합니다.

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