SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The Peripheral Component Interconnect Express (PCIe) subsystem is built around a single-lane dual-mode PCIe controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 5.0 Gbps per lane for serial links on backplanes and printed wiring boards.
The device includes one instantiation the of PCIe subsystem - PCIE0. Table 12-107 shows the PCIe subsystem allocation across device domains.
Module Instance | Domain | |
MCU | MAIN | |
PCIE0 | - | ✓ |
Figure 12-202 provides PCIe subsystem overview.