The Display Subsystem module includes the following features:
- Two display outputs
- Up to 24-bit per pixel arallel or embedded sync output
- Up to 200MHz pizel clock
- Supports
- 1920x1080@60fps
- 1x 2048x1080 + 1x 1280x720 (constrained by DDR bandwidth)
- Support for RGB/YUV422 modes
- Support for progressive/interlaced modes
- Two display pipelines support 2x OpenLDI 4-data/1clk link (either
shared to provide a 4K display or mirroring the same display -
independent displays on each OLDI are not supported)
- Two input display processing pipelines
- One video pipeline supporting full RGB and 8/10-bit YUV data formats
with 3/5-tap 16-phase scaler capable of 0.25x to 16x resizing.
- One video_lite pipeline supporting full RGB and 8/10 YUV data
formats (no resizing support)
- Two Overlay Managers with multi layer alpha blending
- One DMA controller capable of supporting up to 2K input source width.
- 48-bit addressing (256 TB reach)
- On-the-fly X/Y-axis flip of the source (Flip/Mirror mode support)
- Safety check (freeze frame detection and data correctness check)