SPRUJB3
March 2024
AM67
,
AM67A
,
TDA4AEN-Q1
,
TDA4VEN-Q1
1
Read This First
About This Manual
Related Documentation From Texas Instruments
Glossary
Support Resources
Export Control Notice
Release History
Trademarks
1
Introduction
1.1
Overview
1.2
Module Allocation and Instances within Device Domains
1.3
Functional Block Diagram
1.4
Device MAIN Domain
1.4.1
Arm Cortex-A53 Subsystem (A53SS)
1.4.2
Arm Cortex-R5F Processor (R5FSS)
1.4.3
Deep Learning Accelerator (C7x256v)
1.4.4
Vision Pre-processing Accelerator
1.4.5
Depth and Motion Perception Accelerator
1.4.6
Mailbox (MAILBOX)
1.4.7
Spinlock (SPINLOCK)
1.4.8
DDR 32-bit Subsystem (DDR32)
1.4.9
Data Movement Subsystem (DMSS)
1.4.10
General Purpose Input/Output Interface (GPIO)
1.4.11
Inter-Integrated Circuit Interface (I2C)
1.4.12
Serial Peripheral Interface (SPI)
1.4.13
Universal Asynchronous Receiver/Transmitter (UART)
1.4.14
3-port Gigabit Ethernet Switch (CPSW3G)
1.4.15
Universal Serial Bus (USB) Subsystem 2.0
1.4.16
Universal Serial Bus 3.1 Subsystem (USBSS)
1.4.17
Serializer/Deserializer (SERDES)
1.4.18
Peripheral Component Interconnect Express Subsystem (PCIE)
1.4.19
Enhanced Pulse-Width Modulation Module (EPWM)
1.4.20
Enhanced Quadrature Encoder Pulse Module (EQEP)
1.4.21
Enhanced Capture Module (ECAP)
1.4.22
Controller Area Network (MCAN)
1.4.23
Flash Subsystem (FSS) with Octal Serial Peripheral Interface (OSPI)
1.4.24
General Purpose Memory Controller (GPMC)
1.4.25
Error Location Module (ELM)
1.4.26
Multi-Media Card/Secure Digital Interface (MMCSD)
1.4.27
Memory Cyclic Redundancy Check
1.4.28
Windowed Watchdog Timer/Real Time Interrupt
1.4.29
TIMER
1.4.30
Audio Tracking Logic
1.4.31
Camera Subsystem
1.4.32
Dual Clock Comparator
1.4.33
Error Signaling Module (ESM)
1.4.34
Multi-Channel Audio Serial Port (McASP)
1.4.35
Camera Streaming Interface Receiver (CSI-RX)
1.4.36
Display Subsystem (DSS)
1.4.37
Open LVDS Display Interface transmitter (OLDI-TX)
1.4.38
MIPI DPHY Receiver
1.4.39
MIPI DPHY Transmitter
1.4.40
Graphics Processing Unit
1.4.41
Video Accelerator (CODEC)
1.5
Device MCU Domain
1.5.1
Arm Cortex-R5F Processor (R5FSS)
1.5.2
MCU General Purpose Input/Output Interface (MCU_GPIO)
1.5.3
MCU Inter-Integrated Circuit Interface (MCU_I2C)
1.5.4
MCU Multi-channel Serial Peripheral Interface (MCU_SPI)
1.5.5
MCU Universal Asynchronous Receiver/Transmitter (MCU_UART)
1.5.6
MCU Windowed Watchdog Timer/Real Time Interrupt
1.5.7
WKUP TIMER
1.5.8
MCU Dual Clock Comparator
1.5.9
Memory Cyclic Redundancy Check
1.5.10
Controller Area Network (MCAN)
1.6
Device WKUP Domain
1.6.1
Arm Cortex-R5F Processor (R5FSS)
1.6.2
Inter-Integrated Circuit Interface (I2C)
1.6.3
Universal Asynchronous Receiver/Transmitter (UART)
1.6.4
MCU Error Signaling Module
1.6.5
Global Time Counter
1.6.6
Windowed Watchdog Timer/Real Time Interrupt
1.6.7
WKUP_TIMER
1.7
Device Identification
2
Memory Map
2.1
MAIN Memory Map
2.2
MCU Memory Map
2.3
WKUP Memory Map
2.4
R5FSS0 Memory Map
2.5
MCU_R5FSS0 Memory Map
2.6
WKUP_R5FSS0 Memory Map
2.7
DMASS0 Memory Map
2.8
SMS0 Memory Map
2.9
SA3_SS0 Memory Map
3
System Interconnect
3.1
System Interconnect Overview
3.1.1
Terminology
3.2
Domain Partition
3.3
Initiator/Target Connectivity
3.4
Coherency Features
3.4.1
IO Coherency Support
3.5
Performance Tuning
3.5.1
Latency Reduction
3.5.2
Using Quality of Service (QoS) MMR
3.5.2.1
QoS MMR Programming Guide
3.5.2.2
QoS Summary Tables
3.5.2.2.1
CODEC0_QoS_Map
3.5.2.2.2
DEBUGSS_WRAP0_QoS_Map
3.5.2.2.3
COMPUTE_CLUSTER0_QoS_Map
3.5.2.2.4
DSS0_QoS_Map
3.5.2.2.5
DSS1_QoS_Map
3.5.2.2.6
GICSS0_QoS_Map
3.5.2.2.7
GPU0_QoS_Map
3.5.2.2.8
MCU_R5FSS0_QoS_Map
3.5.2.2.9
MMCSD0_QoS_Map
3.5.2.2.10
WKUP_R5FSS0_QoS_Map
3.5.2.2.11
USB0_QoS_Map
3.5.2.2.12
USB1_QoS_Map
3.5.2.2.13
SA3_SS0_QoS_Map
3.5.2.2.14
MMCSD1_QoS_Map
3.5.2.2.15
MMCSD2_QoS_Map
3.6
Interconnect Debugging Feature
4
Module Integration
4.1
Memory Controllers
4.1.1
DDR32 Subsystem (DDR32SS)
4.1.1.1
DDR32SS Not Supported Features
4.1.1.2
DDR32SS Module Allocations
4.1.1.3
Resets, Interrupts and Clocks
4.1.2
msram8kx256e
4.1.2.1
Module Allocations
4.1.2.2
Resets, Interrupts and Clocks
4.2
System Interconnect
4.2.1
CBASS
4.2.1.1
CBASS_AUDIO
4.2.1.1.1
Module Allocations
4.2.1.1.2
Resets, Interrupts, and Clocks
4.2.1.2
CBASS_RT_CFG
4.2.1.2.1
Module Allocations
4.2.1.2.2
Resets, Interrupts, and Clocks
4.2.1.3
CBASS_RT_DATA
4.2.1.3.1
Module Allocations
4.2.1.3.2
Resets, Interrupts, and Clocks
4.2.1.4
CBASS_RT_FW
4.2.1.4.1
Module Allocations
4.2.1.4.2
Resets, Interrupts, and Clocks
4.2.2
C7XV_RSWS_BS_LIMITER
4.2.2.1
Module Allocations
4.2.2.2
Resets, Interrupts, and Clocks
4.2.3
JPGENC_RS_BW_LIMITER
4.2.3.1
Module Allocations
4.2.3.2
Resets, Interrupts, and Clocks
4.2.4
JPGENC_WS_BW_LIMITER
4.2.4.1
Module Allocations
4.2.4.2
Resets, Interrupts, and Clocks
4.2.5
GPU_RS_BW_LIMITER
4.2.5.1
Module Allocations
4.2.5.2
Resets, Interrupts, and Clocks
4.2.6
GPU_WS_BW_LIMITER
4.2.6.1
Module Allocations
4.2.6.2
Resets, Interrupts, and Clocks
4.2.7
VPAC_RSWS_BW_LIMITER
4.2.7.1
Module Allocations
4.2.7.2
Resets, Interrupts, and Clocks
4.3
Processors and Accelerators
4.3.1
Arm Cortex A53 Subsystem (A53SS)
4.3.1.1
A53SS Unsupported Features
4.3.1.2
Module Allocations
4.3.1.3
Resets, Interrupts, and Clocks
4.3.2
WAVE 521CL - CODEC
4.3.2.1
WAVE521CL Unsupported Features
4.3.2.2
Module Allocations
4.3.2.3
Resets, Interrupts, and Clocks
4.3.3
Arm Cortex R5F Subsystem (R5FSS)
4.3.3.1
Module Allocations
4.3.3.2
Resets, Interrupts, and Clocks
4.3.3.3
Arm Cortex R5F Subsystem (MCU_R5FSS)
4.3.3.3.1
MCU_R5FSS Unsupported Features
4.3.3.3.2
Module Allocations
4.3.3.3.3
Resets, Interrupts, and Clocks
4.3.3.4
R5FSS_CORE0
4.3.3.4.1
Module Allocations
4.3.3.4.2
Resets, Interrupts, and Clocks
4.3.3.5
R5FSS_COMMON0
4.3.3.5.1
Module Allocations
4.3.3.5.2
Resets, Interrupts, and Clocks
4.3.4
Vision Pre-processing Accelerator (VPAC)
4.3.4.1
Module Allocations
4.3.4.2
Resets, Interrupts, and Clocks
4.3.5
Depth and Motion Perception Accelerator (DMPAC)
4.3.5.1
Module Allocations
4.3.5.2
Resets, Interrupts, and Clocks
4.3.6
JPGENC
4.3.6.1
Module Allocations
4.3.6.2
Resets, Interrupts, and Clocks
4.3.7
C7X256V
4.3.7.1
Module Allocations
4.3.7.2
Resets, Interrupts, and Clocks
4.3.7.3
C7X256V_C7XV_CORE_0
4.3.7.3.1
Module Allocations
4.3.7.3.2
Resets, Interrupts, and Clocks
4.3.7.4
C7X256V_CORE0
4.3.7.4.1
Module Allocations
4.3.7.4.2
Resets, Interrupts, and Clocks
4.3.7.5
C7X256V_CLEC
4.3.7.5.1
Module Allocations
4.3.7.5.2
Resets, Interrupts, and Clocks
4.3.7.6
C7X256V_PBIST
4.3.7.6.1
Module Allocations
4.3.7.6.2
Resets, Interrupts, and Clocks
4.3.8
Graphics Processing Unit (GPU)
4.3.8.1
GPU Unsupported Features
4.3.8.2
Module Allocations
4.3.8.3
Resets, Interrupts, and Clocks
4.4
Interprocessor Communication
4.4.1
Mailbox
4.4.1.1
Mailbox Unsupported Features
4.4.1.2
Module Allocations
4.4.1.3
Resets, Interrupts, and Clocks
4.4.2
Spinlock
4.4.2.1
SPINLOCK Unsupported Features
4.4.2.2
Module Allocations
4.4.2.3
Resets, Interrupts, and Clocks
4.5
Device Configuration
4.5.1
Control Module (CTRL_MMR)
4.5.1.1
Module Allocations
4.5.1.2
Resets, Interrupts, and Clocks
4.5.1.3
Module Allocations
4.5.1.4
Resets, Interrupts, and Clocks
4.5.2
Voltage and Thermal Manager (VTM)
4.5.2.1
Module Allocations
4.5.2.2
Resets, Interrupts, and Clocks
4.5.3
Power Sleep Controller (PSC)
4.5.3.1
Module Allocations
4.5.3.2
Resets, Interrupts, and Clocks
4.5.4
Clocking
4.5.4.1
pllfracf2_ssmod_16fft
4.5.4.1.1
Module Allocations
4.5.4.1.2
Resets, Interrupts, and Clocks
4.6
Interrupts
4.6.1
TIMESYNC_EVENT_INTROUTER
4.6.1.1
Module Allocations
4.6.1.2
Resets, Interrupts, and Clocks
4.6.2
Generic Interrupt Controller Subsystem (GICSS)
4.6.2.1
GICSS Unsupported Features
4.6.2.2
Module Allocation
4.6.2.3
Resets, Interrupts, and Clocks
4.7
Data Movement Architecture
4.7.1
Data Movement Subsystem (DMSS)
4.7.1.1
DMSS Unsupported Features
4.7.1.2
Module Allocations
4.7.1.3
Global Event Map
4.7.1.4
PSI-L System Thread Map
4.7.2
Block Copy DMA (BCDMA)
4.7.2.1
Block Copy DMA (BCDMA)
4.7.3
Peripheral DMA (PDMA)
4.7.3.1
PDMA Unsupported Features
4.7.3.2
Module Allocations
4.7.3.3
Resets, Interrupts, and Clocks
4.7.4
Packet DMA (PKTDMA)
4.7.4.1
Packet DMA (PKTDMA)
4.7.4.2
Resets, Interrupts, and Clocks
4.8
Audio
4.8.1
Audio Tracking Logic (ATL)
4.8.1.1
ATL Module Allocations
4.8.1.2
Resets, Interrupts, and Clocks
4.8.2
Multichannel Audio Serial Port (MCASP)
4.8.2.1
MCASP Unsupported Features
4.8.2.2
Module Allocations
4.8.2.3
Resets, Interrupts, and Clocks
4.9
General Connectivity
4.9.1
General Purpose Input/Output (GPIO)
4.9.1.1
GPIO Unsupported Features
4.9.1.2
Module Allocation
4.9.1.3
Resets, Interrupts, and Clocks
4.9.2
Inter-Integrated Circiuit (I2C)
4.9.2.1
I2C Unsupported Features
4.9.2.2
Module Allocations
4.9.2.3
Resets, Interrupts, and Clocks
4.9.3
Multichannel Serial Peripheral Interface (MCSPI)
4.9.3.1
MCSPI SPI Unsupported Features
4.9.3.2
Module Allocations
4.9.3.3
Resets, Interrupts, and Clocks
4.9.4
Universal Asynchronous Receiver/Transmitter (UART)
4.9.4.1
UART Unsupported Features
4.9.4.2
Module Allocations
4.9.4.3
Resets, Interrupts, and Clocks
4.10
High-speed Serial Interfaces
4.10.1
Peripheral Component Interconnect Express (PCIe) Subsystem
4.10.1.1
Module Allocations
4.10.1.2
Resets, Interrupts, and Clocks
4.10.2
Gigabit Ethernet Switch (CPSW)
4.10.2.1
CPSW Unsupported Features
4.10.2.2
Module Allocations
4.10.2.3
Resets, Interrupts, and Clocks
4.10.3
Serializer/Deserializer (SerDes)
4.10.3.1
Module Allocations
4.10.3.2
Resets, Interrupts, and Clocks
4.10.4
Universal Serial Bus Subsystem (USB)
4.10.4.1
USB2SS Unsupported Features
4.10.4.2
Module Allocations
4.10.4.3
Resets, Interrupts, and Clocks
4.11
Memory Interfaces
4.11.1
Flash Subsystem (FSS)
4.11.1.1
FSS Unsupported Features
4.11.1.2
Module Allocations
4.11.1.3
Resets, Interrupts, and Clocks
4.11.2
Octal Serial Peripheral Interface (OSPI)
4.11.2.1
OSPI Unsupported Features
4.11.2.2
Module Allocations
4.11.2.3
Resets, Interrupts, and Clocks
4.11.3
General-Purpose Memory Controller (GPMC)
4.11.3.1
GPMC Unsupported Features
4.11.3.2
Module Allocations
4.11.3.3
Resets, Interrupts, and Clocks
4.11.4
Error Location Module (ELM)
4.11.4.1
ELM Unsupported Features
4.11.4.2
Module Allocations
4.11.4.3
Resets, Interrupts, and Clocks
4.11.5
Multimedia Card Secure Digital (MMCSD)
4.11.5.1
MMCSD Unsupported Features
4.11.5.2
Module Allocations
4.11.5.3
Resets, Interrupts, and Clocks
4.12
Industrial and Control Interfaces
4.12.1
Modular Controller Area Network (MCAN)
4.12.1.1
MCAN Unsupported Features
4.12.1.2
Module Allocations
4.12.1.3
Resets, Interrupts, and Clocks
4.12.2
Enhanced Capture (ECAP)
4.12.2.1
ECAP Unsupported Features
4.12.2.2
Module Allocations
4.12.2.3
Resets, Interrupts, and Clocks
4.12.3
Enhanced Pulse Width Modulation (EPWM)
4.12.3.1
EPWM Unsupported Features
4.12.3.2
Module Allocations
4.12.3.3
Resets, Interrupts, and Clocks
4.12.4
Enhanced Quadrature Encoder Pulse (EQEP)
4.12.4.1
EQEP Unsupported Features
4.12.4.2
Module Allocations
4.12.4.3
Resets, Interrupts, and Clocks
4.13
Camera Subsystem
4.13.1
Camera Serial Interface Receiver (CSI_RX_IF)
4.13.1.1
CSI_RX_IF Unsupported Features
4.13.1.2
Module Allocations
4.13.1.3
Resets, Interrupts, and Clocks
4.13.2
MIPI D-PHY Receiver (DPHY_RX)
4.13.2.1
DPHY_RX Unsupported Features
4.13.2.2
Module Allocations
4.13.2.3
Resets, Interrupts, and Clocks
4.13.3
MIPI D-PHY Transmitter (DPHY_TX)
4.13.3.1
DPHY_TX Unsupported Features
4.13.3.2
Module Allocations
4.13.3.3
Resets, Interrupts, and Clocks
4.13.4
Camera Streaming Interface Transmitter (CSI_TX_IF)
4.13.4.1
Module Allocations
4.13.4.2
Resets, Interrupts, and Clocks
4.14
Timer Modules
4.14.1
Global Timebase Counter (GTC)
4.14.1.1
GTC Unsupported Features
4.14.1.2
Module Allocations
4.14.1.3
Resets, Interrupts, and Clocks
4.14.2
Real Time Interrupt (RTI)
4.14.2.1
RTI Unsupported Features
4.14.2.2
Module Allocations
4.14.2.3
Resets, Interrupts, and Clocks
4.14.3
Real-Time Clock (RTC)
4.14.3.1
RTC Unsupported Features
4.14.3.2
Module Allocations
4.14.3.3
Resets, Interrupts, and Clocks
4.14.4
Timer
4.14.4.1
Timer Unsupported Features
4.14.4.2
Module Allocations
4.14.4.3
Resets, Interrupts, and Clocks
4.15
Internal Diagnostic Modules
4.15.1
Dual Clock Comparator (DCC)
4.15.1.1
DCC Unsupported Features
4.15.1.2
Module Allocations
4.15.1.3
Resets, Interrupts, and Clocks
4.15.1.4
DCC Input Source Clock Mapping
4.15.2
Error Signaling Module (ESM)
4.15.2.1
ESM Unsupported Features
4.15.2.2
Module Allocations
4.15.2.3
Resets, Interrupts, and Clocks
4.15.3
Memory Cyclic Redundancy Check (MCRC64)
4.15.3.1
MCRC64 Unsupported Features
4.15.3.2
Module Allocations
4.15.3.3
Resets, Interrupts, and Clocks
4.15.4
Programmable Built-In Self-Test (PBIST)
4.15.4.1
Module Allocations
4.15.4.2
Resets, Interrupts, and Clocks
4.15.5
ECC Aggregator (ECC_AGGR)
4.15.5.1
Module Allocations
4.15.5.2
Resets, Interrupts, and Clocks
4.16
Display Subsystem (DSS)
4.16.1
DSS_UL Unsupported Features
4.16.2
Module Allocations
4.16.3
Resets, Interrupts, and Clocks
4.16.4
oldi_tx_core
4.16.4.1
Module Allocations
4.16.4.2
Resets, Interrupts, and Clocks
4.17
On-Chip Debug
4.17.1
CPT2_PROBE
4.17.1.1
Module Allocations
4.17.1.2
Resets, Interrupts, and Clocks
4.17.2
CTI
4.17.2.1
Module Allocations
4.17.2.2
Resets, Interrupts, and Clocks
5
Initialization
5.1
Initialization Overview
5.1.1
ROM Code Overview
5.1.2
Bootloader Modes
5.1.3
Terminology
5.2
Boot Process
5.2.1
Public ROM Code Architecture
5.2.1.1
Main Module
5.2.1.2
X509 Module
5.2.1.3
Buffer Manager Module
5.2.1.4
Log and Trace Module
5.2.1.5
System Module
5.2.1.6
Protocol Module
5.2.1.7
Driver Module
5.2.2
M4 ROM Description
5.2.3
Boot Process Flow
5.3
Boot Mode Pins
5.3.1
BOOTMODE Pin Mapping
5.3.1.1
Primary Boot Mode Selection and Configuration
5.3.1.2
Backup Boot Mode Selection and Configuration
5.4
Boot Modes
5.4.1
OSPI\xSPI\QSPI\SPI Boot
5.4.1.1
OSPI Boot
5.4.1.1.1
OSPI Bootloader Operation
5.4.1.1.1.1
OSPI Initialization Process
5.4.1.1.1.2
OSPI Loading Process
5.4.1.2
xSPI Boot
5.4.1.2.1
xSPI Bootloader Operation
5.4.1.3
Fast-xSPI Boot Mode Configuration
5.4.1.4
QSPI Boot
5.4.1.4.1
QSPI Bootloader Operation
5.4.1.4.1.1
QSPI Initialization Process
5.4.1.4.1.2
QSPI Loading Process
5.4.1.5
SPI Boot
5.4.1.5.1
SPI Bootloader Operation
5.4.1.5.1.1
SPI Initialization Process
5.4.1.5.1.2
SPI Loading Process
5.4.2
I2C Boot
5.4.2.1
I2C Bootloader Operation
5.4.2.1.1
I2C Initialization Process
5.4.2.1.1.1
Block Size
5.4.2.1.1.2
Addressing
5.4.2.1.2
I2C Loading Process
5.4.2.1.2.1
Loading a Boot Image From EEPROM
5.4.3
SD Card Boot
5.4.3.1
SD Card Bootloader Operation
5.4.4
eMMC Boot
5.4.4.1
eMMC Bootloader Operation
5.4.5
Ethernet Boot
5.4.5.1
Ethernet Bootloader Operation
5.4.5.1.1
Ethernet Initialization Process
5.4.5.1.2
Ethernet Loading Process
5.4.5.1.2.1
Ethernet Boot Data Formats
5.4.5.1.2.1.1
Limitations
5.4.5.1.2.1.2
BOOTP Request
5.4.5.1.2.1.2.1
MAC Header (DIX)
5.4.5.1.2.1.2.2
IPv4 Header
5.4.5.1.2.1.2.3
UDP Header
5.4.5.1.2.1.2.4
BOOTP Payload
5.4.5.1.2.1.2.5
TFTP
5.4.5.1.3
Ethernet Hand Over Process
5.4.6
USB Boot
5.4.6.1
USB Bootloader Operation
5.4.6.1.1
USB-Specific Attributes
5.4.6.1.1.1
DFU Device Mode
5.4.7
UART Boot
5.4.7.1
UART Bootloader Operation
5.4.7.1.1
Initialization Process
5.4.7.1.2
UART Loading Process
5.4.7.1.2.1
UART XMODEM
5.4.7.1.3
UART Hand-Over Process
5.4.8
GPMC NOR Boot
5.4.8.1
GPMC NOR Bootloader Operation
5.4.9
GPMC NAND Boot
5.4.9.1
GPMC NAND Bootloader Operation
5.4.10
Serial NAND Boot
5.4.10.1
Serial NAND Bootloader Operation
5.4.10.2
Serial NAND Initialization Process
5.4.10.3
Serial NAND Loading Process
5.4.11
No boot/Development boot
5.5
PLL Configuration
5.6
Boot Parameter Tables
5.6.1
Common Header
5.6.2
PLL Setup
5.6.3
OSPI/QSPI/SPI Boot Parameter Table
5.6.4
UART Boot Parameter Table
5.6.5
I2C Boot Parameter Table
5.6.6
MMCSD/eMMC Boot Parameter Table
5.6.7
Ethernet Boot Parameter Table
5.6.8
xSPI/Fast-xSPI Boot Parameter Table
5.6.9
USB DFU Boot Parameter Table
5.6.10
USB MSC Boot Parameter Table
5.6.11
GPMC NOR Boot Parameter Table
5.6.12
GPMC NAND Boot Parameter Table
5.7
Boot Image Format
5.7.1
Overall Structure
5.7.2
X.509 Certificate
5.7.3
Organizational Identifier (OID)
5.7.4
X.509 Extensions Specific to Boot
5.7.4.1
Boot Info (OID 1.3.6.1.4.1.294.1.1)
5.7.4.2
Image Integrity (OID 1.3.6.1.4.1.294.1.2)
5.7.5
Extended Boot Info Extension
5.7.5.1
Impact on HS Device
5.7.5.2
Extended Boot Info Details
5.7.5.3
Certificate / Component Types
5.7.5.4
Extended Boot Encryption Info
5.7.5.5
Component Ordering
5.7.5.6
Memory Load Sections Overlap with Executable Components
5.7.5.7
Device Type and Extended Boot Extension
5.7.6
Generating X.509 Certificates
5.7.6.1
Key Generation
5.7.6.1.1
Degenerate RSA Keys
5.7.6.2
Configuration Script
5.7.6.3
Image Data
5.8
Boot Memory Maps
5.8.1
Memory Layout/MPU
5.8.2
Global Memory Addresses Used by ROM Code
6
Device Configuration
6.1
Control Module
6.2
Power
6.3
Reset
6.4
Clocking
7
Processors and Accelerators
7.1
Arm Cortex-A53 Subsystem (A53SS)
7.1.1
A53SS Overview
7.1.1.1
A53SS Introduction
7.1.1.2
A53SS Features
525
7.1.2
A53SS Functional Description
7.1.2.1
A53SS Block Diagram
7.1.2.2
Arm Cortex-A53 Cluster
7.1.2.3
A53SS Interfaces and Async Bridges
7.1.2.4
A53SS Interrupts
7.1.2.4.1
A53SS Interrupt Inputs
7.1.2.4.2
A53SS Interrupt Outputs
7.1.2.5
A53SS Power Management and Clocking
7.1.2.5.1
A53SS Power Management
7.1.2.5.2
A53SS Clocking
7.1.2.6
A53SS Debug
7.1.2.7
A53SS Global and Debug Timestamps
7.1.2.8
A53SS Watchdog
7.1.2.9
A53SS Functional Safety - ECC Error Injection Support
7.1.2.9.1
A53 ECC Aggregators During Low Power States
7.1.2.9.2
Auto-initialization of Memories
7.1.2.9.3
A53 SRAM Safety
7.1.2.9.4
A53 SRAM ECC Aggregator Configurations
7.1.2.10
A53SS Boot
7.1.2.11
A53SS Interprocessor Communication
7.2
Arm Cortex R5F Subsystem (R5FSS)
7.2.1
R5FSS Overview
7.2.1.1
R5FSS Features
7.2.1.2
R5FSS Not Supported Features
7.2.2
R5FSS Functional Description
7.2.2.1
R5FSS Block Diagram
7.2.2.2
R5FSS Cortex-R5F Core
7.2.2.2.1
L1 Caches
7.2.2.2.2
Tightly-Coupled Memories (TCMs)
7.2.2.2.3
R5FSS Special Signals
7.2.2.3
R5FSS Interfaces
7.2.2.3.1
Initiator Interfaces
7.2.2.3.2
Target Interfaces
7.2.2.4
R5FSS Power, Clocking and Reset
7.2.2.4.1
R5FSS Power
7.2.2.4.2
R5FSS Clocking
7.2.2.4.3
R5FSS Reset
7.2.2.5
R5FSS Vectored Interrupt Manager (VIM)
7.2.2.5.1
VIM Overview
7.2.2.5.2
VIM Interrupt Inputs
7.2.2.5.3
VIM Interrupt Outputs
7.2.2.5.4
VIM Interrupt Vector Table (VIM RAM)
7.2.2.5.5
VIM Interrupt Prioritization
7.2.2.5.6
VIM ECC Support
7.2.2.5.7
VIM IDLE State
7.2.2.5.8
VIM Interrupt Handling
7.2.2.5.8.1
Servicing IRQ Through Vector Interface
7.2.2.5.8.2
Servicing IRQ Through MMR Interface
7.2.2.5.8.3
Servicing IRQ Through MMR Interface (Alternative)
7.2.2.5.8.4
Servicing FIQ
7.2.2.5.8.5
Servicing FIQ (Alternative)
7.2.2.6
R5FSS Region Address Translation (RAT)
7.2.2.7
R5FSS ECC Support
7.2.2.8
R5FSS Memory View
7.2.2.9
R5FSS Interrupts
7.2.2.10
R5FSS Debug and Trace
7.2.2.11
R5FSS Boot Options
7.2.2.12
R5FSS Core Memory ECC Events
7.3
Cortex R5F Subsystem (R5FSS)
7.3.1
R5FSS Overview
7.3.1.1
R5FSS Features
587
7.3.2
R5FSS Functional Description
7.3.2.1
R5FSS Block Diagram
7.3.2.2
R5FSS Cortex-R5F Core
7.3.2.2.1
L1 Caches
7.3.2.2.2
Tightly-Coupled Memories (TCMs)
7.3.2.2.3
R5FSS Special Signals
7.3.2.3
R5FSS Interfaces
7.3.2.3.1
Initiator Interfaces
7.3.2.3.2
Target Interfaces
7.3.2.4
R5FSS Power, Clocking and Reset
7.3.2.4.1
R5FSS Power
7.3.2.4.2
R5FSS Clocking
7.3.2.4.3
R5FSS Reset
7.3.2.5
R5FSS Vectored Interrupt Manager (VIM)
7.3.2.5.1
VIM Overview
7.3.2.5.2
VIM Interrupt Inputs
7.3.2.5.3
VIM Interrupt Outputs
7.3.2.5.4
VIM Interrupt Vector Table (VIM RAM)
7.3.2.5.5
VIM Interrupt Prioritization
7.3.2.5.6
VIM ECC Support
7.3.2.5.7
VIM IDLE State
7.3.2.5.8
VIM Interrupt Handling
7.3.2.5.8.1
Servicing IRQ Through Vector Interface
7.3.2.5.8.2
Servicing IRQ Through MMR Interface
7.3.2.5.8.3
Servicing IRQ Through MMR Interface (Alternative)
7.3.2.5.8.4
Servicing FIQ
7.3.2.5.8.5
Servicing FIQ (Alternative)
7.3.2.6
R5FSS Region Address Translation (RAT)
7.3.2.6.1
WKUP R5FSS Usage
7.3.2.6.2
RAT Function
7.3.2.6.3
How to use RAT Block in R5
7.3.2.6.4
Example of Using RAT to Access Full 36b SoC Memory Map
7.3.2.7
R5FSS ECC Support
7.3.2.8
R5FSS Memory View
7.3.2.9
R5FSS Interrupts
7.3.2.10
R5FSS Debug and Trace
7.3.2.11
R5FSS Boot Options
7.3.2.12
R5FSS Core Memory ECC Events
7.3.3
Vectored Interrupt Manager (VIM)
7.3.3.1
VIM Overview
7.3.3.1.1
VIM Features
7.3.3.1.2
Unsupported Features
630
7.3.3.2
VIM Functional Description
7.3.3.2.1
Block Diagram
7.3.3.2.2
Interrupt Inputs
7.3.3.2.3
Interrupt Outputs
7.3.3.2.4
Priority Interrupt / Nested Interrupts
7.3.3.2.5
VIC Port
7.3.3.2.6
Latency
7.3.3.2.7
Safety
7.3.3.2.8
IDLE
7.3.3.3
Interrupt Conditions
7.3.3.3.1
CPU Interrupts
7.3.3.3.2
Interrupt Description
7.3.3.3.2.1
coreN_IRQn
7.3.3.3.2.2
coreN_FIQn
7.3.3.3.3
Interrupt Condition Control
7.3.3.3.3.1
coreN_IRQn
7.3.3.3.3.2
coreN_FIQn
7.3.3.3.4
Interrupt Handling
7.3.3.3.4.1
IRQ through the Vector Interface
7.3.3.3.4.2
IRQ through MMR Interface
7.3.3.3.4.3
IRQ through MMR Interface (Alternative)
7.3.3.3.4.4
FIQ
7.3.3.3.4.5
FIQ (Alternative)
7.3.3.4
Memory Map
7.3.3.5
Module I/O
7.3.3.5.1
Clocks, Reset, Emulation
7.3.3.5.2
VBUSP Target Interface
7.3.3.5.3
Interrupt Inputs
7.3.3.5.4
Interrupt Outputs
7.3.3.5.5
VIC Interfaces
7.3.3.5.6
Compare Outputs
7.3.3.5.7
ECC Control and Status Bus
7.3.3.5.8
DFT
7.3.3.5.9
RAM GPIO
7.3.3.6
Programmer's Guide
7.3.3.6.1
Initialization Sequence
7.3.3.6.2
DED Behavior
7.3.3.6.3
Power Up/Down Sequence
7.4
Device Manager Cortex R5F Subsystem (WKUP_R5FSS)
7.4.1
WKUP_R5FSS Overview
7.4.1.1
WKUP_R5FSS Features
672
7.4.2
WKUP_R5FSS Functional Description
7.4.2.1
WKUP_R5FSS Block Diagram
7.4.2.2
WKUP_R5FSS Cortex-R5F Core
7.4.2.2.1
L1 Caches
7.4.2.2.2
Tightly-Coupled Memories (TCMs)
7.4.2.2.3
WKUP_R5FSS Special Signals
7.4.2.3
WKUP_R5FSS Interfaces
7.4.2.3.1
Initiator Interfaces
7.4.2.3.2
Target Interfaces
7.4.2.4
WKUP_R5FSS Power, Clocking and Reset
7.4.2.4.1
WKUP_R5FSS Power
7.4.2.4.2
WKUP_R5FSS Clocking
7.4.2.4.3
WKUP_R5FSS Reset
7.4.2.5
WKUP_R5FSS Vectored Interrupt Manager (VIM)
7.4.2.5.1
VIM Overview
7.4.2.5.2
VIM Interrupt Inputs
7.4.2.5.3
VIM Interrupt Outputs
7.4.2.5.4
VIM Interrupt Vector Table (VIM RAM)
7.4.2.5.5
VIM Interrupt Prioritization
7.4.2.5.6
VIM ECC Support
7.4.2.5.7
VIM IDLE State
7.4.2.5.8
VIM Interrupt Handling
7.4.2.5.8.1
Servicing IRQ Through Vector Interface
7.4.2.5.8.2
Servicing IRQ Through MMR Interface
7.4.2.5.8.3
Servicing IRQ Through MMR Interface (Alternative)
7.4.2.5.8.4
Servicing FIQ
7.4.2.5.8.5
Servicing FIQ (Alternative)
7.4.2.6
WKUP_R5FSS Region Address Translation (RAT)
7.4.2.6.1
WKUP R5FSS Usage
7.4.2.6.2
RAT Function
7.4.2.6.3
How to use RAT Block in R5
7.4.2.6.4
Example of Using RAT to Access Full 36b SoC Memory Map
7.4.2.7
WKUP_R5FSS ECC Support
7.4.2.8
WKUP_R5FSS Memory View
7.4.2.9
WKUP_R5FSS Interrupts
7.4.2.10
WKUP_R5FSS Debug and Trace
7.4.2.11
WKUP_R5FSS Boot Options
7.4.2.12
WKUP_R5FSS Core Memory ECC Events
7.5
Vectored Interrupt Manager (VIM)
7.5.1
VIM Overview
7.5.1.1
VIM Features
7.5.1.2
Unsupported Features
715
7.5.2
VIM Functional Description
7.5.2.1
Block Diagram
7.5.2.2
Interrupt Inputs
7.5.2.3
Interrupt Outputs
7.5.2.4
Priority Interrupt / Nested Interrupts
7.5.2.5
VIC Port
7.5.2.6
Latency
7.5.2.7
Safety
7.5.2.8
IDLE
7.5.3
Interrupt Conditions
7.5.3.1
CPU Interrupts
7.5.3.2
Interrupt Description
7.5.3.2.1
coreN_IRQn
7.5.3.2.2
coreN_FIQn
7.5.3.3
Interrupt Condition Control
7.5.3.3.1
coreN_IRQn
7.5.3.3.2
coreN_FIQn
7.5.3.4
Interrupt Handling
7.5.3.4.1
IRQ through the Vector Interface
7.5.3.4.2
IRQ through MMR Interface
7.5.3.4.3
IRQ through MMR Interface (Alternative)
7.5.3.4.4
FIQ
7.5.3.4.5
FIQ (Alternative)
7.5.4
Memory Map
7.5.5
VIM Registers
7.5.5.1
Revision Register (Base Address + 0x00)
7.5.5.2
Info Register (Base Address + 0x04)
7.5.5.3
Prioritized IRQ (Base Address + 0x08)
7.5.5.4
Prioritized FIQ (Base Address + 0x0C)
7.5.5.5
IRQ Group Status (Base Address + 0x10)
7.5.5.6
FIQ Group Status (Base Address + 0x14)
7.5.5.7
IRQ Vector Address (Base Address + 0x18)
7.5.5.8
FIQ Vector Address (Base Address + 0x1C)
7.5.5.9
Active IRQ (Base Address + 0x20)
7.5.5.10
Active FIQ (Base Address + 0x24)
7.5.5.11
IRQ Priority Mask Register (Base Address + 0x28)
7.5.5.12
FIQ Priority Mask Register (Base Address + 0x2C)
7.5.5.13
DED Vector Address (Base Address + 0x30)
7.5.5.14
Group M Interrupt Raw Status/Set Register (Base Address + 0x400 + M*0x20 + 0x00)
7.5.5.15
Group M Interrupt Enabled Status/Clear Register (Base Address + 0x400 + M*0x20 + 0x04)
7.5.5.16
Group M Interrupt Enabled Set Register (Base Address + 0x400 + M*0x20 + 0x08)
7.5.5.17
Group M Interrupt Enabled Clear Register (Base Address + 0x400 + M*0x20 + 0x0C)
7.5.5.18
Group M Interrupt IRQ Enabled Status/Clear Register (Base Address + 0x400 + M*0x20 + 0x10)
7.5.5.19
Group M Interrupt FIQ Enabled Status/Clear Register (Base Address + 0x400 + M*0x20 + 0x14)
7.5.5.20
Group M Interrupt Map Register (Base Address + 0x400 + M*0x20 + 0x18)
7.5.5.21
Group M Type Map Register (Base Address + 0x400 + M*0x20 + 0x1C)
7.5.5.22
Interrupt Q Priority Register (Base Address + 0x1000 + Q*0x4)
7.5.5.23
Interrupt Q Vector Register (Base Address + 0x2000 + Q*0x4)
7.5.6
Module I/O
7.5.6.1
Clocks, Reset, Emulation
7.5.6.2
VBUSP Target Interface
7.5.6.3
Interrupt Inputs
7.5.6.4
Interrupt Outputs
7.5.6.5
VIC Interfaces
7.5.6.6
Compare Outputs
7.5.6.7
ECC Control and Status Bus
7.5.6.8
DFT
7.5.6.9
RAM GPIO
7.5.7
Programmer's Guide
7.5.7.1
Initialization Sequence
7.5.7.2
DED Behavior
7.5.7.3
Power Up/Down Sequence
7.6
Video Encoder/Decoder (VENC/VDEC)
7.6.1
Introduction
7.6.2
Features
7.6.2.1
Performance
7.6.2.2
Codec Related Features
7.6.2.3
Non-Codec Related Features
7.6.3
Block Diagram
7.7
Vision Pre-processing Accelerator (VPAC)
7.7.1
VPAC Overview
7.7.1.1
VPAC Features
7.7.2
VPAC Subsystem Level
7.7.2.1
VPAC Subsystem Clocks
7.7.2.2
VPAC Subsystem Resets
7.7.2.3
VPAC Subsystem Interrupts
7.7.2.4
VPAC Subsystem SL2 Memory Infrastructure
7.7.2.5
VPAC Subsystem DMA Infrastructure
7.7.2.6
VPAC Subsystem Data Formats Support
7.7.2.7
VPAC Subsystem Debug Features
7.7.2.8
VPAC Subsystem Security Features
7.7.3
VPAC Vision Imaging Subsystem (VISS)
7.7.3.1
VISS Top Level
7.7.3.1.1
VISS Features
7.7.3.1.2
VISS Block Diagram
7.7.3.1.3
VISS Data Flow within VPAC
7.7.3.1.3.1
VISS On-the-fly Processing
7.7.3.1.3.1.1
Non-WDR or Companded WDR Sensors
7.7.3.1.3.2
VISS Memory to Memory Image Processing
7.7.3.1.4
VISS Data Formats Support
7.7.3.1.5
VISS VPORT Interface
7.7.3.1.6
VISS Submodule Integration Specifics
7.7.3.1.6.1
LSE Integration
7.7.3.1.6.2
PCID
7.7.3.1.6.3
GLBCE Integration
7.7.3.1.6.3.1
GLBCE Startup
7.7.3.1.6.3.2
GLBCE Bypass
7.7.3.1.7
VISS Stall Handling
7.7.3.1.7.1
Stall Handling for Streaming Mode
7.7.3.1.8
VISS Interrupts
7.7.3.1.8.1
Interrupts Merging
7.7.3.1.8.2
Handling of Configuration Error Interrupts
7.7.3.1.9
VISS Error Correcting Code (ECC) Support
7.7.3.1.10
VISS Programmer's Guide
7.7.3.1.10.1
VISS Initialization Sequence
7.7.3.1.10.2
VISS Configuration Restrictions
7.7.3.1.10.3
VISS Real-time Operating Requirements
7.7.3.2
VISS Load Store Engine (LSE)
7.7.3.3
VISS RAW Frond-End (RAWFE)
7.7.3.3.1
RAWFE Overview
7.7.3.3.1.1
RAWFE Supported Features
7.7.3.3.2
RAWFE Functional Description
7.7.3.3.2.1
RAWFE Functional Operation
7.7.3.3.2.2
RAWFE ECC for RAMs
7.7.3.3.3
RAWFE Interrupts
7.7.3.3.3.1
RAWFE CPU Interrupts
7.7.3.3.3.2
RAWFE Debug Events
7.7.3.3.4
RAWFE Sub-Modules Details
7.7.3.3.4.1
RAWFE Decompanding Block
7.7.3.3.4.1.1
RAWFE Mask & Shift
7.7.3.3.4.1.2
RAWFE Piece Wise Linear Operation
7.7.3.3.4.1.3
RAWFE Offset/WB-1 Block
7.7.3.3.4.1.4
RAWFE LUT Based compression
7.7.3.3.4.2
RAWFE WDR Merge Block
7.7.3.3.4.2.1
RAWFE WDR Motion Adaptive Merge (MA1 / MA2)
7.7.3.3.4.2.2
RAWFE Companding LUT
7.7.3.3.4.3
RAWFE Defective Pixel Correction (DPC) Block for 2x2 Bayer CFA
7.7.3.3.4.3.1
RAWFE LUT Based DPC
7.7.3.3.4.3.2
RAWFE On-The-Fly (OTF) DPC
7.7.3.3.4.4
RAWFE Lens Shading Correction (LSC) and Digital Gain (DG) Block
7.7.3.3.4.4.1
RAWFE LSC Features Supported
7.7.3.3.4.4.2
RAWFE LSC Image Framing with Respect to Gain Map Samples
7.7.3.3.4.5
RAWFE Gain & Offset Block
7.7.3.3.4.6
RAWFE H3A
7.7.3.3.4.6.1
RAWFE H3A Overview
7.7.3.3.4.6.2
RAWFE H3A Top-Level Block Diagram
7.7.3.3.4.6.3
RAWFE H3A Line Framing Logic
7.7.3.3.4.6.4
RAWFE H3A Optional Preprocessing
7.7.3.3.4.6.5
RAWFE H3A Autofocus Engine
7.7.3.3.4.6.5.1
RAWFE H3A Paxel Extraction
7.7.3.3.4.6.5.2
RAWFE H3A Horizontal FV Calculator
7.7.3.3.4.6.5.3
RAWFE H3A HFV Accumulator
7.7.3.3.4.6.5.4
RAWFE H3A VFV Calculator
7.7.3.3.4.6.5.5
RAWFE H3A VFV Accumulator
7.7.3.3.4.6.6
RAWFE H3A AE/AWB Engine
7.7.3.3.4.6.6.1
RAWFE H3A Subsampler
7.7.3.3.4.6.6.2
RAWFE H3A Additional Black Row of AE/AWB Windows
7.7.3.3.4.6.6.3
RAWFE H3A Saturation Check
7.7.3.3.4.6.6.4
RAWFE H3A AE/AWB Accumulators
7.7.3.3.4.6.7
RAWFE H3A DMA Interface
7.7.3.3.4.6.8
RAWFE H3A Events and Status Checking
7.7.3.3.4.6.9
RAWFE H3A Interface Mux
7.7.3.3.4.6.10
RAWFE H3A interface to LSE
7.7.3.3.4.6.11
RAWFE H3A Erratas
7.7.3.3.5
RAWFE Programmer’s Guide
7.7.3.3.5.1
RAWFE Core programming details
7.7.3.3.5.2
RAWFE Initialization Sequence
7.7.3.3.5.3
RAWFE Real-time Оperating Requirements
7.7.3.3.6
Pattern Conversion and IR Demosaicing (PCID) Module
7.7.3.3.6.1
Overview and Feature List
7.7.3.3.6.1.1
PCID Features Supported
7.7.3.3.6.1.2
Functional Operation
7.7.3.3.6.1.3
Calculation of pixel level IR subtraction factors
7.7.3.4
VISS Spatial Noise Filter (NSF4V)
7.7.3.4.1
NSF4V Introduction
7.7.3.4.1.1
NSF4V Features
7.7.3.4.1.2
NSF4V Not Supported Features
7.7.3.4.2
NSF4V Overview
7.7.3.4.2.1
Decomposition Kernel Representation
7.7.3.4.3
NSF4V Lens Shading Correction Compensation
7.7.3.4.4
NSF4V Noise Threshold Adaptation to Local Image Intensity
7.7.3.5
VISS Global/Local Brightness and Contrast Enhancement (GLBCE) Module
7.7.3.5.1
GLBCE Overview
7.7.3.5.2
GLBCE Interface
7.7.3.5.3
GLBCE Core
7.7.3.5.3.1
GLBCE Core Key Parameters
7.7.3.5.3.2
GLBCE Iridix Strength Calculation
7.7.3.5.3.3
GLBCE Iridix Configuration Registers
7.7.3.5.3.3.1
GLBCE Iridix Frame Width
7.7.3.5.3.3.2
GLBCE Iridix Frame Height
7.7.3.5.3.3.3
GLBCE Iridix Control 0
7.7.3.5.3.3.4
GLBCE Iridix Control 1
7.7.3.5.3.3.5
GLBCE Iridix Strength
7.7.3.5.3.3.6
GLBCE Iridix Variance
7.7.3.5.3.3.7
GLBCE Iridix Dither
7.7.3.5.3.3.8
GLBCE Iridix Amplification Limit
7.7.3.5.3.3.9
GLBCE Iridix Slope Min and Max
7.7.3.5.3.3.10
GLBCE Iridix Black Level
7.7.3.5.3.3.11
GLBCE Iridix White Level
7.7.3.5.3.3.12
GLBCE Iridix Asymmetry Function Look-up-table
7.7.3.5.3.3.13
GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
7.7.3.5.3.3.14
GLBCE Iridix WDR Look-up-table
7.7.3.5.4
GLBCE Embedded Memory
7.7.3.5.5
GLBCE General Processing
7.7.3.5.6
GLBCE Continuous Frame Processing
7.7.3.5.7
GLBCE Single Image Processing
7.7.3.6
VISS Flexible Color Processing (FCP) Module
7.7.3.6.1
FCP Overview
7.7.3.6.1.1
FCP Features Supported
7.7.3.6.2
FCP Functional Description
7.7.3.6.3
FCP Submodule Details
7.7.3.6.3.1
Flexible CFA / Demosaicing
7.7.3.6.3.1.1
Feature-set
7.7.3.6.3.1.2
Block Diagram of Flexible CFA
7.7.3.6.3.1.2.1
Gradient/Threshold Calculation
7.7.3.6.3.1.2.2
Software Controlled Direction Selection
7.7.3.6.3.2
Edge Enhancer Module Wrapper (WEE)
7.7.3.6.3.2.1
EE - Edge Enhancer Block
7.7.3.6.3.3
Flexible Color Conversion (CC)
7.7.3.6.3.3.1
Interface Mux
7.7.3.6.3.3.2
Color Conversion (CCM-1)
7.7.3.6.3.3.3
RGB to HSX Conversion
7.7.3.6.3.3.3.1
Weighted Average Block
7.7.3.6.3.3.3.2
Saturation Block
7.7.3.6.3.3.3.3
Division Block
7.7.3.6.3.3.3.4
LUT Based 12 to 8 Downsampling
7.7.3.6.3.3.4
Histogram
7.7.3.6.3.3.5
Contrast Stretch / Gamma
7.7.3.6.3.3.6
RGB-YUV Conversion
7.7.3.6.3.4
444-422/420 Chroma Down-sampler
7.7.3.6.4
FCP Interrupts
7.7.3.6.5
FCP Programmer’s Guide
7.7.3.6.5.1
HWA Core Programming Details
7.7.3.6.5.2
HWA HTS Programming Details
7.7.3.6.5.3
HWA Data Transfer Programming Details
7.7.3.6.5.4
Initialization Sequence
7.7.3.6.5.5
Real-time Operating Requirements
7.7.3.6.5.6
Power Up/Down Sequence
7.7.3.7
VISS Edge Enhancer (EE)
7.7.3.7.1
Edge Enhancer Introduction
7.7.3.7.1.1
Edge Enhancer Filter
7.7.3.7.1.2
Edge Sharpener Filter
7.7.3.7.1.3
Merge Block
7.7.3.7.2
Edge Enhancer Programming Model
7.7.4
VPAC Lens Distortion Correction (LDC) Module
7.7.4.1
LDC Overview
7.7.4.1.1
LDC Features
7.7.4.2
LDC Functional Description
7.7.4.2.1
LDC Block Diagram
7.7.4.2.2
LDC Clocks
7.7.4.2.3
LDC Interrupts
7.7.4.2.3.1
LDC Interrupt Events Description
7.7.4.2.3.1.1
PIX_IBLK_OUTOFBOUND
7.7.4.2.3.1.2
MESH_IBLK_OUTOFBOUND
7.7.4.2.3.1.3
IFR_OUTOFBOUND
7.7.4.2.3.1.4
INT_SZOVF
7.7.4.2.3.1.5
VPAC_LDC_FR_DONE_EVT
7.7.4.2.3.1.6
VPAC_LDC_SL2_WR_ERR
7.7.4.2.3.1.7
PIX_IBLK_MEMOVF
7.7.4.2.3.1.8
MESH_IBLK_MEMOVF
7.7.4.2.3.1.9
VPAC_LDC_VBUSM_RD_ERR
7.7.4.2.4
LDC Affine Transform
7.7.4.2.5
LDC Perspective Transformation
7.7.4.2.6
LDC Lens Distortion Back Mapping
7.7.4.2.6.1
LDC Mesh Table Storage Format
7.7.4.2.7
LDC Pixel Interpolation
7.7.4.2.8
LDC Buffer Management
7.7.4.2.8.1
LDC Buffer Management
7.7.4.2.9
LDC Multi Region with Variable Block size
7.7.4.2.9.1
LDC Region Skip Feature
7.7.4.2.9.2
LDC Support for sub-set of 3x3 regions
7.7.4.2.9.3
LDC Limitations of Multi Region Scheme
7.7.4.2.9.4
LDC Multi Region Block Constrains
7.7.4.2.10
LDC Multi-pass Frame processing
7.7.4.2.11
LDC Input/Output Data Formats
7.7.4.2.12
LDC YUV422 to YUV420 Conversion
7.7.4.2.13
LDC SL2 Interface (LSE)
7.7.4.2.13.1
LDC PSA (Parallel Signature Analysis)
7.7.4.2.14
LDC LUT Mapped Dual Output
7.7.4.2.15
LDC Band Width Controller
7.7.4.2.16
LDC Input Block Fetch Limit
7.7.4.2.17
LDC HTS Interface
7.7.4.2.18
LDC VBUSM Read Interface
7.7.4.3
LDC Programmers Guide
7.7.4.3.1
LDC Programming Geometric Distortion Mode
7.7.4.3.2
LDC Programming Rotational Video Stabilization (Affine Transformation)
7.7.4.3.3
LDC Programming Perspective Transformation
7.7.4.3.4
LDC Programming LSE
7.7.4.3.5
LDC Programming Restrictions and Special Cases
7.7.5
VPAC Multi-Scaler (MSC)
7.7.5.1
MSC Overview
7.7.5.1.1
MSC Features
7.7.5.1.2
MSC Not Supported Features
7.7.5.2
MSC Functional Description
7.7.5.2.1
MSC Functional Overview
7.7.5.2.1.1
MSC Submodule Details
7.7.5.2.1.1.1
MSC Load Store Engine (MSC_LSE)
7.7.5.2.1.1.1.1
MSC_LSE Overview
7.5.2.1.1.1.1.1
MSC_LSE Features
7.7.5.2.1.1.1.2
MSC_LSE Internal Data Loopback Channel
7.7.5.2.1.1.1.3
MSC_LSE PSA Support
7.7.5.2.1.1.1.4
MSC_LSE Feature Detailed Description
7.7.5.2.1.1.2
MSC_CORE (HWA Core)
7.7.5.2.1.1.2.1
MSC_CORE Overview
7.7.5.2.1.1.2.2
Polyphase Filter of Vertical/Horizontal Resizers
7.5.2.1.1.2.2.1
Filter Data Path Logic
7.5.2.1.1.2.2.2
Filter Parameters
7.5.2.1.1.2.2.3
Single-Phase Filter Parameters
7.5.2.1.1.2.2.4
Interleaved Mode Handling
7.5.2.1.1.2.2.5
Input Skip Line Support
7.7.5.2.1.1.2.3
Scaler Filter Thread Mapping
7.7.5.2.1.1.2.4
Filter Coefficients
7.5.2.1.1.2.4.1
Filter Coefficient Parameter Configuration
7.5.2.1.1.2.4.2
3/4/5-Tap Filter Configuration
7.7.5.2.1.1.2.5
Input/Output ROI Trimmers
7.7.5.2.2
Resizer Algorithm Details
7.7.5.2.2.1
Multiple Scales Generations
7.7.5.2.2.2
Polyphase Filter
7.7.5.2.2.2.1
Interpolation/Resampling
7.7.5.2.2.2.2
Phase Calculation and Re-sampler
7.7.5.2.2.2.3
Shared Coefficient Buffers
7.7.5.2.2.2.4
Border Pixel Padding
7.7.5.2.2.3
ROI Handling
7.7.5.2.3
MSC Data Formats Supported
7.7.5.3
MSC Interrupt Conditions
7.7.5.3.1
CPU Interrupts
7.7.5.3.2
Interrupt Event Description
7.7.5.3.2.1
VPAC_MSC_LSE_FR_DONE_EVT_0/1 Events
7.7.5.3.2.2
VPAC_MSC_LSE_SL2_RD_ERR Interrupt Event
7.7.5.3.2.3
VPAC_MSC_LSE_SL2_WR_ERR Interrupt Event
7.7.5.4
MSC Performance
7.7.5.5
MSC Clocking
7.7.5.6
MSC Reset
7.7.5.7
MSC Programmer’s Guide
7.7.5.7.1
Programming Model
7.7.5.7.1.1
MSC Programming Guidelines
7.7.5.7.1.2
MSC_Core Programming Details
7.7.5.7.1.3
MSC_LSE Programming Details
7.7.5.7.1.3.1
Input Thread Configuration:
7.7.5.7.1.3.2
Output Channel Configuration
7.7.5.7.1.4
MSC HTS Programming Details
7.7.5.7.1.5
MSC Data Transfer Programming Details
7.7.5.7.1.6
LSE Interrupt Programming
7.7.5.7.2
Initialization Sequence
7.7.5.7.3
Real-Time Operating Requirements
7.7.5.7.4
Power Up/Down Sequence
7.8
Depth and Motion Perception Accelerator (DMPAC)
7.8.1
DMPAC Overview
7.8.1.1
DMPAC Features
7.9
Graphics Accelerator (GPU)
7.9.1
GPU Overview
7.9.1.1
Features Supported
1058
7.9.1.2
Unsupported Features
8
Inter-processor Communication Scheme (IPC)
8.1
Mailbox
8.1.1
Mailbox Overview
8.1.1.1
Mailbox Features
1064
8.1.2
Mailbox Functional Description
8.1.2.1
Mailbox Block Diagram
8.1.2.2
Mailbox Software Reset
8.1.2.3
Mailbox Power Management
8.1.2.4
Mailbox Interrupt Requests
8.1.2.5
Mailbox Assignment
8.1.2.5.1
Description
8.1.2.6
Sending and Receiving Messages
8.1.2.6.1
Description
8.1.2.7
Example of Communication
8.1.3
Mailbox Programming Guide
8.1.3.1
Mailbox Low-level Programming Models
8.1.3.1.1
Global Initialization
8.1.3.1.1.1
Surrounding Modules Global Initialization
8.1.3.1.1.2
Mailbox Global Initialization
8.1.3.1.1.2.1
Main Sequence - Mailbox Global Initialization
8.1.3.1.2
Mailbox Operational Modes Configuration
8.1.3.1.2.1
Mailbox Processing modes
8.1.3.1.2.1.1
Main Sequence - Sending a Message (Polling Method)
8.1.3.1.2.1.2
Main Sequence - Sending a Message (Interrupt Method)
8.1.3.1.2.1.3
Main Sequence - Receiving a Message (Polling Method)
8.1.3.1.2.1.4
Main Sequence - Receiving a Message (Interrupt Method)
8.1.3.1.3
Mailbox Events Servicing
8.1.3.1.3.1
Events Servicing in Sending Mode
8.1.3.1.3.2
Events Servicing in Receiving Mode
8.2
Spinlock
8.2.1
Spinlock Overview
1092
8.2.2
Spinlock Functional Description
8.2.2.1
Spinlock Software Reset
8.2.2.2
Spinlock Power Management
8.2.2.3
About Spinlocks
8.2.2.4
Spinlock Functional Operation
8.2.3
Spinlock Programming Guide
8.2.3.1
Spinlock Low-level Programming Models
8.2.3.1.1
Surrounding Modules Global Initialization
8.2.3.1.2
Basic Spinlock Operations
8.2.3.1.2.1
Spinlocks Clearing After a System Bug Recovery
8.2.3.1.2.2
Take and Release Spinlock
8.3
Secure Proxy (SEC_PROXY)
9
Memory Controllers
9.1
DDR Subsystem (DDRSS)
9.1.1
DDRSS Overview
1108
9.1.2
DDRSS Environment
9.1.3
DDRSS Functional Description
9.1.3.1
Real Time and Non-Real Time Threads
9.1.3.2
Class of Service (CoS)
9.1.3.3
AXI Write Data All-Strobes
9.1.3.4
Inline ECC for SDRAM Data
9.1.3.4.1
ECC Cache
9.1.3.4.2
ECC Cache Flush
9.1.3.4.3
ECC Statistics
9.1.3.5
Address Alias Prevention
9.1.3.6
AXI Bus Timeout
9.1.3.7
Leaky Bucket Function
9.1.3.8
Drain Function
9.1.3.9
DDRSS Interrupts
9.1.3.10
DDRSS Memory Regions
9.1.3.11
DDRSS Dynamic Frequency Change Interface
9.1.3.12
DDR Controller Functional Description
9.1.3.12.1
DDR PHY Interface (DFI)
9.1.3.12.2
Command Queue
9.1.3.12.2.1
Placement Logic
9.1.3.12.2.2
Command Selection Logic
9.1.3.12.3
Transaction Processing
9.1.3.12.4
Paging Policy
9.1.3.12.5
DDR Controller Initialization
10
Interrupts
10.1
Interrupt Architecture
10.1.1
ESM Connectivity
10.1.1.1
Using WKUP_ESM to Monitor All Error Events in SoC
10.1.1.2
Using MAIN_ESM to Monitor All Error Interrupts in SoC
10.1.1.3
ESM Configuration During Deep Sleep Mode
10.1.2
PSIL Events
10.1.3
GPIO Interrupt Handling
10.1.4
Utilizing Miscellaneous Signals as Interrupt
10.1.4.1
Aggregated Interrupt from Timeout Gasket
10.1.4.2
Aggregated DCC Interrupt
10.1.4.3
Aggregated Access Error Interrupt from CBASS
10.1.4.4
Access Error to Control Register Block Interrupt Aggregation
10.2
Interrupt Controllers
10.2.1
Generic Interrupt Controller (GICSS)
10.2.1.1
GICSS Overview
10.2.1.1.1
GICSS Features
1150
10.2.1.1.2
Unsupported Features
10.2.1.2
GICSS Integration
10.2.1.3
GICSS Functional Description
10.2.1.3.1
GICSS Block Diagram
10.2.1.3.2
Arm GIC-500
10.2.1.3.3
GICSS Interrupt Types
10.2.1.3.4
GICSS Interfaces
10.2.1.3.5
GICSS Interrupt Outputs
10.2.1.3.6
GICSS ECC Support
10.2.1.3.7
GICSS AXI2VBUSM and VBUSM2AXI Bridges
10.3
Interrupt Router (INTROUTER)
10.3.1
INTROUTER Integration
10.4
Interrupt Sources
10.4.1
C7X256V0_CLEC_INTERRUPT_MAP
10.4.2
C7X256V1_CLEC_INTERRUPT_MAP
10.4.3
COMPUTE_CLUSTER0_INTERRUPT_MAP
10.4.4
CPSW0_INTERRUPT_MAP
10.4.5
DMASS0_INTAGGR_0_INTERRUPT_MAP
10.4.6
EPWM0_INTERRUPT_MAP
10.4.7
EPWM1_INTERRUPT_MAP
10.4.8
EPWM2_INTERRUPT_MAP
10.4.9
ESM0_INTERRUPT_MAP
10.4.10
GICSS0_INTERRUPT_MAP
10.4.11
GLUELOGIC_A53_EVENTI_GLUE_INTERRUPT_MAP
10.4.12
GLUELOGIC_EPWM0_SYNC_MUXGLUE_INTERRUPT_MAP
10.4.13
GLUELOGIC_GLUE_EXT_INTN_INTERRUPT_MAP
10.4.14
GLUELOGIC_MAIN_DCC_DONE_GLUE_INTERRUPT_MAP
10.4.15
GLUELOGIC_MCU_ACCESS_ERR_INTR_GLUE_INTERRUPT_MAP
10.4.16
GLUELOGIC_MCU_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
10.4.17
GLUELOGIC_MGASKET_INTR_GLUE_INTERRUPT_MAP
10.4.18
GLUELOGIC_PWM_TRIP_OR_GLUE_INTERRUPT_MAP
10.4.19
GLUELOGIC_SGASKET_INTR_GLUE_INTERRUPT_MAP
10.4.20
GLUELOGIC_SOC_ACCESS_ERR_INTR_GLUE_INTERRUPT_MAP
10.4.21
GLUELOGIC_SOC_CBASS_ERR_INTR_GLUE_INTERRUPT_MAP
10.4.22
GLUELOGIC_WKUP_PBIST_CPUINTR_INTERRUPT_MAP
10.4.23
GLUELOGICN_LBIST_DONE_GLUE_INTERRUPT_MAP
10.4.24
GLUELOGICN_MAIN_PBIST_CPU_GLUE_INTERRUPT_MAP
10.4.25
HSM0_INTERRUPT_MAP
10.4.26
MAIN_GPIOMUX_INTROUTER0_INTERRUPT_MAP
10.4.27
MCU_R5FSS0_CORE0_INTERRUPT_MAP
10.4.28
PCIE0_INTERRUPT_MAP
10.4.29
PDMA0_INTERRUPT_MAP
10.4.30
PDMA1_INTERRUPT_MAP
10.4.31
PDMA2_INTERRUPT_MAP
10.4.32
PDMA3_INTERRUPT_MAP
10.4.33
PINFUNCTION_CP_GEMAC_CPTS0_TS_COMPOUT_INTERRUPT_MAP
10.4.34
PINFUNCTION_CP_GEMAC_CPTS0_TS_SYNCOUT_INTERRUPT_MAP
10.4.35
PINFUNCTION_SYNC0_OUTOUT_INTERRUPT_MAP
10.4.36
PINFUNCTION_SYNC1_OUTOUT_INTERRUPT_MAP
10.4.37
PINFUNCTION_SYNC2_OUTOUT_INTERRUPT_MAP
10.4.38
PINFUNCTION_SYNC3_OUTOUT_INTERRUPT_MAP
10.4.39
R5FSS0_CORE0_INTERRUPT_MAP
10.4.40
SMS0_COMMON_0_INTERRUPT_MAP
10.4.41
TIFS0_INTERRUPT_MAP
10.4.42
TIMESYNC_EVENT_INTROUTER0_INTERRUPT_MAP
10.4.43
USB0_INTERRUPT_MAP
10.4.44
WKUP_DEEPSLEEP_SOURCES0_INTERRUPT_MAP
10.4.45
WKUP_ESM0_INTERRUPT_MAP
10.4.46
WKUP_MCU_GPIOMUX_INTROUTER0_INTERRUPT_MAP
10.4.47
WKUP_R5FSS0_CORE0_INTERRUPT_MAP
11
Data Movement Architecture
11.1
Data Movement Architecture Overview
11.1.1
Overview
11.1.1.1
Ring Accelerator (RINGACC)
11.1.1.2
Secure Proxy (SEC_PROXY)
11.1.1.3
Interrupt Aggregator (INTAGGR)
11.1.1.4
Packet DMA (PKTDMA)
11.1.1.4.1
PKTDMA Submodule Descriptions
11.1.1.4.1.1
Bus Interface Unit
11.1.1.4.1.2
Config CR
11.1.1.4.1.3
Configuration Registers
11.1.1.4.1.3.1
RX State Mapping
11.1.1.4.1.3.2
TX State Mapping
11.1.1.4.1.4
Tx Packet DMA Unit
11.1.1.4.1.5
Tx Packet Coherency Unit
11.1.1.4.1.6
Tx Per Channel Buffers
11.1.1.4.1.7
Rx Per Channel Buffers
11.1.1.4.1.8
Rx Packet DMA Unit
11.1.1.4.1.9
Rx Packet Coherency Unit
11.1.1.4.1.10
Event Handler
11.1.1.4.2
Channel Classes
11.1.1.5
Block Copy DMA (BCDMA)
11.1.1.5.1
BCDMA Submodule Descriptions
11.1.1.5.1.1
Bus Interface Unit
11.1.1.5.1.2
Config CR
11.1.1.5.1.3
Configuration Registers
11.1.1.5.1.3.1
BCDMA Mapping Table
11.1.1.5.1.4
Read Unit(s)
11.1.1.5.1.5
TR Coherency Unit
11.1.1.5.1.6
Per-Copy-Channel Buffers
11.1.1.5.1.7
Tx Per-Split-Channel Buffers
11.1.1.5.1.8
Rx Per-Split-Channel Buffers
11.1.1.5.1.9
Write Unit(s)
11.1.1.5.1.10
Event Coherency Unit
11.1.1.5.1.11
Event Handler
11.1.1.5.2
Channel Classes
11.1.2
Definition of Terms
11.1.3
DMSS Hardware/Software Interface
11.1.3.1
Data Buffers
11.1.3.2
Descriptors
11.1.3.2.1
Host Packet Descriptor
11.1.3.2.2
Host Buffer Descriptor
11.1.3.2.3
Transfer Request Descriptor
11.1.3.3
Transfer Request Record
11.1.3.3.1
Overview
11.1.3.3.2
Addressing Algorithm
11.1.3.3.2.1
Linear Addressing (Forward)
11.1.3.3.3
Transfer Request Formats
11.1.3.3.4
Flags Field Definition
11.1.3.3.4.1
Type: TR Type Field
11.1.3.3.4.2
EVENT_SIZE: Event Generation Definition
11.1.3.3.4.3
TRIGGER_INFO: TR Triggers
11.1.3.3.4.4
TRIGGERX_TYPE: Trigger Type
11.1.3.3.4.5
TRIGGERX: Trigger Selection
11.1.3.3.4.6
Configuration Specific Flags Definition
11.1.3.3.5
TR Address and Size Attributes
11.1.3.3.5.1
ICNT0
11.1.3.3.5.2
ICNT1
11.1.3.3.5.3
ADDR
11.1.3.3.5.4
DIM1
11.1.3.3.5.5
ICNT2
11.1.3.3.5.6
ICNT3
11.1.3.3.5.7
DIM2
11.1.3.3.5.8
DIM3
11.1.3.3.5.9
DDIM1
11.1.3.3.5.10
DADDR
11.1.3.3.5.11
DDIM2
11.1.3.3.5.12
DDIM3
11.1.3.3.5.13
DICNT0
11.1.3.3.5.14
DICNT1
11.1.3.3.5.15
DICNT2
11.1.3.3.5.16
DICNT3
11.1.3.4
Transfer Response Record
11.1.3.4.1
STATUS Field Definition
11.1.3.4.1.1
STATUS_TYPE Definitions
11.1.3.4.1.1.1
Transfer Error
11.1.3.4.1.1.2
Aborted Error
11.1.3.4.1.1.3
Submission Error
11.1.3.4.1.1.4
Unsupported Feature
11.1.3.4.1.1.5
Transfer Exception
11.1.3.4.1.1.6
Teardown Flush
11.1.3.5
Channels
11.1.3.6
Flows
11.1.3.7
Queues
11.1.3.7.1
Queue Types
11.1.3.7.1.1
Transmit Queues
11.1.3.7.1.2
Transmit Completion Queues
11.1.3.7.1.3
Free Descriptor / Buffer Queues
11.1.3.7.1.4
Receive Queues
11.1.3.7.1.5
Ring Based Queues Implementation
11.1.4
Operational Description
11.1.4.1
Resource Allocation
11.1.4.2
PKTDMA/BCDMA - Ring Operation
11.1.4.2.1
Queue Initialization
11.1.4.2.2
Queueing Entries
11.1.4.2.3
De-queueing Entries
11.1.4.3
PKTDMA/BCDMA - Output Event Generation
11.1.4.4
PKTDMA - Transmit Channel Setup
11.1.4.5
PKTDMA - Transmit Channel Pause
11.1.4.6
PKTDMA - Transmit Channel Teardown
11.1.4.7
PKTDMA - Transmit Operation
11.1.4.8
PKTDMA - Receive Free Descriptor / Buffer Queue Setup
11.1.4.9
PKTDMA - Receive Channel Setup
11.1.4.10
PKTDMA - Receive Channel Teardown
11.1.4.11
PKTDMA - Receive Channel Pause
11.1.4.12
PKTDMA - Receive Operation
11.1.4.13
BCDMA - Block Copy Channel Setup
11.1.4.14
BCDMA - Block Copy Channel Pause
11.1.4.15
BCDMA - Block Copy Channel Teardown
11.1.4.16
BCDMA - Block Copy Operation (TR Packet)
11.1.4.17
BCDMA - Block Copy Error/Exception Handling
11.1.4.17.1
Null Icnt0 Error
11.1.4.17.2
Unsupported TR Type
11.1.4.17.3
Bus Errors
11.1.4.18
BCDMA - Split Transmit Channel Setup
11.1.4.19
BCDMA - Split Transmit Operation Pause
11.1.4.20
BCDMA - Split Transmit Channel Teardown
11.1.4.21
BCDMA - Split Transmit Operation (TR Packet)
11.1.4.22
BCDMA - Split Transmit Error / Exception Handling
11.1.4.22.1
Null Icnt0 Error
11.1.4.22.2
Unsupported TR Type
11.1.4.22.3
Bus Errors
11.1.4.23
BCDMA - Split Receive Channel Setup
11.1.4.24
BCDMA - Split Receive Channel Pause
11.1.4.25
BCDMA - Split Receive Channel Teardown
11.1.4.26
BCDMA - Split Receive Operation (TR Packet)
11.1.4.27
BCDMA - Split Receive Error / Exception Handling
11.1.4.27.1
PKTDMA Exception Conditions
11.1.4.27.1.1
Descriptor Starvation
11.1.4.27.1.2
Protocol Errors
11.1.4.27.1.3
Dropped Packets
11.1.4.27.1.4
Long Packet
11.1.4.27.2
BCDMA Exception Conditions
11.1.4.27.2.1
Reception of EOL Delimiter
11.1.4.27.2.2
EOP Asserted Prematurely (Short Packet)
11.1.4.27.2.3
EOP Asserted Late (Long Packets)
11.1.4.27.2.4
Descriptor Starvation
11.2
Data Movement Subsystem (DMSS)
11.2.1
Data Movement Subsystem (DMSS)
11.2.1.1
DMSS Overview
1351
11.2.1.2
DMSS Functional Description
11.2.1.3
DMSS Interrupt Configuration
11.2.1.3.1
DMSS Event and Interrupt Flow
11.2.1.3.1.1
DMSS Interrupt Description
11.2.1.3.1.2
DMSS Event Description
11.2.2
Ring Accelerator (RINGACC)
11.2.2.1
RINGACC Overview
11.2.2.1.1
RINGACC Features
1360
11.2.2.1.2
RINGACC Parameters
11.2.2.2
RINGACC Functional Description
11.2.2.2.1
Block Diagram
11.2.2.2.1.1
Configuration Registers
11.2.2.2.1.2
Source Command FIFO
11.2.2.2.1.3
Source Write Data FIFO
11.2.2.2.1.4
Source Read Data FIFO
11.2.2.2.1.5
Source Write Status FIFO
11.2.2.2.1.6
Main State Machine
11.2.2.2.1.7
Destination Command FIFO
11.2.2.2.1.8
Destination Write Data FIFO
11.2.2.2.1.9
Destination Read Data FIFO
11.2.2.2.1.10
Destination Write Status FIFO
11.2.2.2.2
RINGACC Functional Operation
11.2.2.2.2.1
Queue Modes
11.2.2.2.2.1.1
Ring Mode
11.2.2.2.2.1.2
Messaging Mode
11.2.2.2.2.1.3
Credentials Mode
11.2.2.2.2.1.4
Peek Support
11.2.2.2.2.1.5
Index Register Operation
11.2.2.2.2.2
VBUSM Target Ring Operations
11.2.2.2.2.3
VBUSM Initiator Interface Command ID Selection
11.2.2.2.2.4
Ring Push Operation (VBUSM Write to Source Interface)
11.2.2.2.2.5
Ring Pop Operation (VBUSM Read from Source Interface)
11.2.2.2.2.6
Host Doorbell Access
11.2.2.2.2.7
Queue Push Operation (VBUSM Write to Source Interface)
11.2.2.2.2.8
Queue Pop Operation (VBUSM Read from Source Interface)
11.2.2.2.2.9
Mismatched Element Size Handling
11.2.2.2.3
Events
11.2.2.2.4
Bus Error Handling
11.2.2.2.5
Monitors
11.2.2.2.5.1
Threshold Monitor
11.2.2.2.5.2
Watermark Monitor
11.2.2.2.5.3
Starvation Monitor
11.2.2.2.5.4
Statistics Monitor
11.2.2.2.5.5
Overflow
11.2.2.2.5.6
Ring Update Port
11.2.2.2.5.7
Tracing
11.2.3
Secure Proxy (SEC_PROXY)
11.2.3.1
Secure Proxy Overview
11.2.3.1.1
Secure Proxy Features
11.2.3.1.2
Secure Proxy Parameters
1403
11.2.3.2
Secure Proxy Functional Description
11.2.3.2.1
Targets
11.2.3.2.1.1
Ring Accelerator
11.2.3.2.2
Buffers
11.2.3.2.3
Proxy Credits
11.2.3.2.4
Proxy Private Word
11.2.3.2.5
Completion Byte
11.2.3.2.6
Proxy Thread Sizes
11.2.3.2.7
Proxy Thread Interleaving
11.2.3.2.8
Proxy States
11.2.3.2.9
Proxy Host Access
11.2.3.2.10
Proxy Host Writes
11.2.3.2.11
Proxy Host Reads
11.2.3.2.12
Buffer Accesses
11.2.3.2.13
Target Access
11.2.3.2.14
Error State
11.2.3.2.15
Permission Inheritance
11.2.3.2.16
Resource Association
11.2.3.2.17
Direction
11.2.3.2.18
Threshold Events
11.2.3.2.19
Error Events
11.2.3.2.20
Bus Error and Credits
11.2.3.2.21
Debug
11.2.4
Interrupt Aggregator (INTAGGR)
11.2.4.1
INTAGGR Overview
11.2.4.1.1
INTAGGR Features
1430
11.2.4.1.2
INTAGGR Parameters
11.2.4.2
INTAGGR Functional Description
11.2.4.2.1
Submodule Descriptions
11.2.4.2.1.1
Status/Mask Registers
11.2.4.2.1.2
Interrupt Mapping Block
11.2.4.2.1.3
Global Event Input (GEVI) Counters
11.2.4.2.1.4
Local Event Input (LEVI) to Global Event Conversion
11.2.4.2.1.5
Global Event Multicast
11.2.4.2.2
General Functionality
11.2.4.2.2.1
Event to Interrupt Bit Steering
11.2.4.2.2.2
Interrupt Status
11.2.4.2.2.3
Interrupt Masked Status
11.2.4.2.2.4
Enabling/Disabling Individual Interrupt Source Bits
11.2.4.2.2.5
Global Event Counting
11.2.4.2.2.6
Local Event to Global Event Conversion
11.2.4.2.2.7
Global Event Multicast
11.2.5
Packet Streaming Interface Link (PSI-L)
11.2.5.1
PSI-L Overview
11.2.5.2
PSI-L Functional Description
11.2.5.2.1
PSI-L Introduction
11.2.5.2.2
PSI-L Operation
11.2.5.2.3
Event Transport
11.2.5.2.4
Threads
11.2.5.2.5
Arbitration Protocol
11.2.5.2.6
Thread Configuration
11.2.5.2.6.1
Thread Pairing
11.2.5.2.6.1.1
Configuration Transaction Pairing
11.2.5.2.6.2
Configuration Registers Region
11.3
Peripheral DMA (PDMA)
11.3.1
PDMA Controller
11.3.1.1
PDMA Overview
11.3.1.1.1
PDMA Features
11.3.1.1.1.1
PDMA0 - SPI Features
11.3.1.1.1.2
PDMA1 - UART Features
11.3.1.1.1.3
PDMA2 - McASP Features
1466
11.3.1.2
Functional Description - SPI
11.3.1.2.1
Compliance to Standards
11.3.1.2.2
Functional Operation
11.3.1.2.2.1
Submodule Descriptions
11.3.1.2.2.1.1
Scheduler
11.3.1.2.2.1.2
Tx Per Channel Buffers
11.3.1.2.2.1.3
Tx DMA Unit
11.3.1.2.2.1.4
Rx Per Channel Buffers
11.3.1.2.2.1.5
Rx DMA Unit
11.3.1.2.2.2
General Functionality (Applicable to All Functions/Modes)
11.3.1.2.2.2.1
Operational States
11.3.1.2.2.2.2
Clock Stop
11.3.1.2.2.2.3
Emulation Control
11.3.1.2.2.2.4
Dynamic Clock Gating
11.3.1.2.2.3
Events and Flow Control
11.3.1.2.2.3.1
Channel Triggering
11.3.1.2.2.3.2
Completion Events
11.3.1.2.2.3.3
Channel Types
11.3.1.2.2.3.3.1
X-Y FIFO Mode
11.3.1.2.2.3.3.2
MCAN Mode
11.3.1.2.2.3.3.3
AASRC Mode
11.3.1.2.2.4
Transmit Operation
11.3.1.2.2.4.1
Destination (Tx) Channel Allocation
11.3.1.2.2.4.2
Destination (Tx) Channel Out of Band Signals
11.3.1.2.2.4.3
Destination Channel Initialization
11.3.1.2.2.4.3.1
PSI-L Destination Thread Pairing Registers
3.1.2.2.4.3.1.1
Enable Register (PSIL Address 0x002)
3.1.2.2.4.3.1.2
Local Capabilities Register (PSIL Address 0x040)
11.3.1.2.2.4.3.2
PSI-L Destination Thread Pairing
11.3.1.2.2.4.3.3
PSI-L Destination Thread Realtime Enable/Count Registers
3.1.2.2.4.3.3.1
RT Enable Register (PSIL Address 0x408)
3.1.2.2.4.3.3.2
Destination Thread Byte Count Register (PSIL Address 0x404)
11.3.1.2.2.4.3.4
Static Transfer Request Setup
3.1.2.2.4.3.4.1
X-Y FIFO Mode Static TR
3.1.2.2.4.3.4.2
MCAN Mode Static TR
3.1.2.2.4.3.4.3
AASRC Mode Static TR
3.1.2.2.4.3.4.4
AASRC TxFifoConfig (PSIL Address 0x405)
3.1.2.2.4.3.4.5
AASRC TxOrderTable0 (PSIL Address 0x406)
3.1.2.2.4.3.4.6
AASRC TxOrderTable1 (PSIL Address 0x407)
11.3.1.2.2.4.3.5
PSI-L Destination Thread Enables
11.3.1.2.2.4.4
Data Transfer
11.3.1.2.2.4.4.1
X-Y FIFO Mode Channel
3.1.2.2.4.4.1.1
X-Y FIFO Burst Mode
11.3.1.2.2.4.4.2
MCAN Mode Channel
3.1.2.2.4.4.2.1
MCAN Burst Mode
11.3.1.2.2.4.4.3
AASRC Channel
11.3.1.2.2.4.5
Transmit PSI-L Interface Transactions
11.3.1.2.2.4.6
Tx Pause
11.3.1.2.2.4.7
Tx Teardown
11.3.1.2.2.4.8
Tx Channel Reset
11.3.1.2.2.4.9
Tx Debug/State Register
11.3.1.2.2.5
Receive Operation
11.3.1.2.2.5.1
Source (Rx) Channel Allocation
11.3.1.2.2.5.2
Source Channel Initialization
11.3.1.2.2.5.2.1
PSI-L Source Thread Pairing Registers
3.1.2.2.5.2.1.1
Peer Thread ID Register (PSIL Address 0x000)
3.1.2.2.5.2.1.2
Peer Credit Register (PSIL Address 0x001)
3.1.2.2.5.2.1.3
Enable Register (PSIL Address 0x002)
11.3.1.2.2.5.2.2
PSI-L Source Thread Realtime Enable/Count Registers
3.1.2.2.5.2.2.1
RT Enable Register (PSIL Address 0x408)
3.1.2.2.5.2.2.2
Source Thread Byte Count Register (PSIL Address 0x404)
11.3.1.2.2.5.2.3
PSI-L Source Thread Pairing
11.3.1.2.2.5.2.4
Static Transfer Request Setup
3.1.2.2.5.2.4.1
X-Y FIFO Mode Static TR
3.1.2.2.5.2.4.2
MCAN Mode Static TR
3.1.2.2.5.2.4.3
AASRC Mode Static TR
3.1.2.2.5.2.4.4
AASRC RxFifoConfig (PSIL Address 0x405)
3.1.2.2.5.2.4.5
AASRC RxOrderTable0 (PSIL Address 0x406)
3.1.2.2.5.2.4.6
AASRC RxOrderTable1 (PSIL Address 0x407)
11.3.1.2.2.5.2.5
PSI-L Source Thread Enables
11.3.1.2.2.5.3
Data Transfer
11.3.1.2.2.5.3.1
X-Y FIFO Mode Channel
3.1.2.2.5.3.1.1
X-Y FIFO Burst Mode
11.3.1.2.2.5.3.2
MCAN Mode Channel
3.1.2.2.5.3.2.1
MCAN Burst Mode
11.3.1.2.2.5.3.3
AASRC Channel
11.3.1.2.2.5.4
Receive PSI-L Interface Transactions
11.3.1.2.2.5.5
Rx Pause
11.3.1.2.2.5.6
Rx Teardown
11.3.1.2.2.5.7
Rx Channel Reset
11.3.1.2.2.5.8
Rx Debug/State Register
11.3.1.3
Functional Description - UART
11.3.1.3.1
Compliance to Standards
11.3.1.3.2
Functional Operation
11.3.1.3.2.1
Submodule Descriptions
11.3.1.3.2.1.1
Scheduler
11.3.1.3.2.1.2
Tx Per Channel Buffers
11.3.1.3.2.1.3
Tx DMA Unit
11.3.1.3.2.1.4
Rx Per Channel Buffers
11.3.1.3.2.1.5
Rx DMA Unit
11.3.1.3.2.2
General Functionality (Applicable to All Functions/Modes)
11.3.1.3.2.2.1
Operational States
11.3.1.3.2.2.2
Clock Stop
11.3.1.3.2.2.3
Emulation Control
11.3.1.3.2.2.4
Dynamic Clock Gating
11.3.1.3.2.3
Events and Flow Control
11.3.1.3.2.3.1
Channel Triggering
11.3.1.3.2.3.2
Completion Events
11.3.1.3.2.3.3
Channel Types
11.3.1.3.2.3.3.1
X-Y FIFO Mode
11.3.1.3.2.3.3.2
MCAN Mode
11.3.1.3.2.3.3.3
AASRC Mode
11.3.1.3.2.4
Transmit Operation
11.3.1.3.2.4.1
Destination (Tx) Channel Allocation
11.3.1.3.2.4.2
Destination (Tx) Channel Out of Band Signals
11.3.1.3.2.4.3
Destination Channel Initialization
11.3.1.3.2.4.3.1
PSI-L Destination Thread Pairing Registers
3.1.3.2.4.3.1.1
Enable Register (PSIL Address 0x002)
3.1.3.2.4.3.1.2
Local Capabilities Register (PSIL Address 0x040)
11.3.1.3.2.4.3.2
PSI-L Destination Thread Pairing
11.3.1.3.2.4.3.3
PSI-L Destination Thread Realtime Enable/Count Registers
3.1.3.2.4.3.3.1
RT Enable Register (PSIL Address 0x408)
3.1.3.2.4.3.3.2
Destination Thread Byte Count Register (PSIL Address 0x404)
11.3.1.3.2.4.3.4
Static Transfer Request Setup
3.1.3.2.4.3.4.1
X-Y FIFO Mode Static TR
3.1.3.2.4.3.4.2
MCAN Mode Static TR
3.1.3.2.4.3.4.3
AASRC Mode Static TR
3.1.3.2.4.3.4.4
AASRC TxFifoConfig (PSIL Address 0x405)
3.1.3.2.4.3.4.5
AASRC TxOrderTable0 (PSIL Address 0x406)
3.1.3.2.4.3.4.6
AASRC TxOrderTable1 (PSIL Address 0x407)
11.3.1.3.2.4.3.5
PSI-L Destination Thread Enables
11.3.1.3.2.4.4
Data Transfer
11.3.1.3.2.4.4.1
X-Y FIFO Mode Channel
3.1.3.2.4.4.1.1
X-Y FIFO Burst Mode
11.3.1.3.2.4.4.2
MCAN Mode Channel
3.1.3.2.4.4.2.1
MCAN Burst Mode
11.3.1.3.2.4.4.3
AASRC Channel
11.3.1.3.2.4.5
Transmit PSI-L Interface Transactions
11.3.1.3.2.4.6
Tx Pause
11.3.1.3.2.4.7
Tx Teardown
11.3.1.3.2.4.8
Tx Channel Reset
11.3.1.3.2.4.9
Tx Debug/State Register
11.3.1.3.2.5
Receive Operation
11.3.1.3.2.5.1
Source (Rx) Channel Allocation
11.3.1.3.2.5.2
Source Channel Initialization
11.3.1.3.2.5.2.1
PSI-L Source Thread Pairing Registers
3.1.3.2.5.2.1.1
Peer Thread ID Register (PSIL Address 0x000)
3.1.3.2.5.2.1.2
Peer Credit Register (PSIL Address 0x001)
3.1.3.2.5.2.1.3
Enable Register (PSIL Address 0x002)
11.3.1.3.2.5.2.2
PSI-L Source Thread Realtime Enable/Count Registers
3.1.3.2.5.2.2.1
RT Enable Register (PSIL Address 0x408)
3.1.3.2.5.2.2.2
Source Thread Byte Count Register (PSIL Address 0x404)
11.3.1.3.2.5.2.3
PSI-L Source Thread Pairing
11.3.1.3.2.5.2.4
Static Transfer Request Setup
3.1.3.2.5.2.4.1
X-Y FIFO Mode Static TR
3.1.3.2.5.2.4.2
MCAN Mode Static TR
3.1.3.2.5.2.4.3
AASRC Mode Static TR
3.1.3.2.5.2.4.4
AASRC RxFifoConfig (PSIL Address 0x405)
3.1.3.2.5.2.4.5
AASRC RxOrderTable0 (PSIL Address 0x406)
3.1.3.2.5.2.4.6
AASRC RxOrderTable1 (PSIL Address 0x407)
11.3.1.3.2.5.2.5
PSI-L Source Thread Enables
11.3.1.3.2.5.3
Data Transfer
11.3.1.3.2.5.3.1
X-Y FIFO Mode Channel
3.1.3.2.5.3.1.1
X-Y FIFO Burst Mode
11.3.1.3.2.5.3.2
MCAN Mode Channel
3.1.3.2.5.3.2.1
MCAN Burst Mode
11.3.1.3.2.5.3.3
AASRC Channel
11.3.1.3.2.5.4
Receive PSI-L Interface Transactions
11.3.1.3.2.5.5
Rx Pause
11.3.1.3.2.5.6
Rx Teardown
11.3.1.3.2.5.7
Rx Channel Reset
11.3.1.3.2.5.8
Rx Debug/State Register
11.3.1.4
Functional Description - McASP
11.3.1.4.1
Compliance to Standards
11.3.1.4.2
Functional Operation
11.3.1.4.2.1
Submodule Descriptions
11.3.1.4.2.1.1
Scheduler
11.3.1.4.2.1.2
Tx Per Channel Buffers
11.3.1.4.2.1.3
Tx DMA Unit
11.3.1.4.2.1.4
Rx Per Channel Buffers
11.3.1.4.2.1.5
Rx DMA Unit
11.3.1.4.2.2
General Functionality (Applicable to All Functions/Modes)
11.3.1.4.2.2.1
Operational States
11.3.1.4.2.2.2
Clock Stop
11.3.1.4.2.2.3
Emulation Control
11.3.1.4.2.3
Events and Flow Control
11.3.1.4.2.3.1
Channel Triggering
11.3.1.4.2.3.2
Completion Events
11.3.1.4.2.3.3
Channel Types
11.3.1.4.2.3.3.1
X-Y FIFO Mode
11.3.1.4.2.3.3.2
MCAN Mode
11.3.1.4.2.3.3.3
AASRC Mode
11.3.1.4.2.4
Transmit Operation
11.3.1.4.2.4.1
Destination (Tx) Channel Allocation
11.3.1.4.2.4.2
Destination (Tx) Channel Out of Band Signals
11.3.1.4.2.4.3
Destination Channel Initialization
11.3.1.4.2.4.3.1
PSI-L Destination Thread Pairing Registers
3.1.4.2.4.3.1.1
Enable Register (PSIL Address 0x002)
3.1.4.2.4.3.1.2
Peer Credit Register (PSIL Address 0x040)
11.3.1.4.2.4.3.2
PSI-L Destination Thread Pairing
11.3.1.4.2.4.3.3
PSI-L Destination Thread Realtime Enable/Count Registers
3.1.4.2.4.3.3.1
RT Enable Register (PSIL Address 0x408)
3.1.4.2.4.3.3.2
Destination Thread Byte Count Register (PSIL Address 0x404)
11.3.1.4.2.4.3.4
Static Transfer Request Setup
3.1.4.2.4.3.4.1
X-Y FIFO Mode Static TR
3.1.4.2.4.3.4.2
MCAN Mode Static TR
3.1.4.2.4.3.4.3
AASRC Mode Static TR
3.1.4.2.4.3.4.4
AASRC TxFifoConfig (PSIL Address 0x405)
3.1.4.2.4.3.4.5
AASRC TxOrderTable0 (PSIL Address 0x406)
3.1.4.2.4.3.4.6
AASRC TxOrderTable1 (PSIL Address 0x407)
11.3.1.4.2.4.3.5
PSI-L Destination Thread Enables
11.3.1.4.2.4.4
Data Transfer
11.3.1.4.2.4.4.1
X-Y FIFO Mode Channel
3.1.4.2.4.4.1.1
X-Y FIFO Burst Mode
11.3.1.4.2.4.4.2
MCAN Mode Channel
11.3.1.4.2.4.4.3
AASRC Channel
11.3.1.4.2.4.5
Transmit PSI-L Interface Transactions
11.3.1.4.2.4.6
Tx Pause
11.3.1.4.2.4.7
Tx Teardown
11.3.1.4.2.4.8
Tx Channel Reset
11.3.1.4.2.4.9
Tx Debug/State Register
11.3.1.4.2.5
Receive Operation
11.3.1.4.2.5.1
Source (Rx) Channel Allocation
11.3.1.4.2.5.2
Source Channel Initialization
11.3.1.4.2.5.2.1
PSI-L Source Thread Pairing Registers
3.1.4.2.5.2.1.1
Peer Thread ID Register (PSIL Address 0x000)
3.1.4.2.5.2.1.2
Peer Credit Register (PSIL Address 0x001)
3.1.4.2.5.2.1.3
Enable Register (PSIL Address 0x002)
11.3.1.4.2.5.2.2
PSI-L Source Thread Realtime Enable/Count Registers
3.1.4.2.5.2.2.1
RT Enable Register (PSIL Address 0x408)
3.1.4.2.5.2.2.2
Source Thread Byte Count Register (PSIL Address 0x404)
11.3.1.4.2.5.2.3
PSI-L Source Thread Pairing
11.3.1.4.2.5.2.4
Static Transfer Request Setup
3.1.4.2.5.2.4.1
X-Y FIFO Mode Static TR
3.1.4.2.5.2.4.2
MCAN Mode Static TR
3.1.4.2.5.2.4.3
AASRC Mode Static TR
3.1.4.2.5.2.4.4
AASRC RxFifoConfig (PSIL Address 0x405)
3.1.4.2.5.2.4.5
AASRC RxOrderTable0 (PSIL Address 0x406)
3.1.4.2.5.2.4.6
AASRC RxOrderTable1 (PSIL Address 0x407)
11.3.1.4.2.5.2.5
PSI-L Source Thread Enables
11.3.1.4.2.5.3
Data Transfer
11.3.1.4.2.5.3.1
X-Y FIFO Mode Channel
3.1.4.2.5.3.1.1
X-Y FIFO Burst Mode
11.3.1.4.2.5.3.2
MCAN Mode Channel
11.3.1.4.2.5.3.3
AASRC Channel
11.3.1.4.2.5.4
Receive PSI-L Interface Transactions
11.3.1.4.2.5.5
Rx Pause
11.3.1.4.2.5.6
Rx Teardown
11.3.1.4.2.5.7
Rx Channel Reset
11.3.1.4.2.5.8
Rx Debug/State Register
12
Peripherals
12.1
General Connectivity Peripherals
12.1.1
General-Purpose Interface (GPIO)
12.1.1.1
GPIO Overview
12.1.1.1.1
GPIO Features
12.1.1.1.2
Unsupported Features
1713
12.1.1.2
GPIO Environment
12.1.1.2.1
GPIO Interface Signals
12.1.1.3
Integration
12.1.1.4
GPIO Functional Description
12.1.1.4.1
GPIO Block Diagram
12.1.1.4.2
GPIO Function
12.1.1.4.3
Interrupt and Event Generation
12.1.1.4.3.1
Interrupt Enable (per Bank)
12.1.1.4.3.2
Trigger Configuration (per Bit)
12.1.1.4.3.3
Interrupt Status and Clear (per Bit)
12.1.1.4.4
GPIO Interrupt Connectivity
12.1.1.4.5
Emulation Halt Operation
12.1.1.5
GPIO Programming Guide
12.1.1.5.1
GPIO Low-Level Programming Models
12.1.1.5.1.1
Global Initialization
12.1.1.5.1.1.1
Surrounding Modules Global Initialization
12.1.1.5.1.1.2
GPIO Module Global Initialization
12.1.1.5.1.2
GPIO Operational Modes Configuration
12.1.1.5.1.2.1
GPIO Read Input Register
12.1.1.5.1.2.2
GPIO Set Bit Function
12.1.1.5.1.2.3
GPIO Clear Bit Function
12.1.2
Inter-Integrated Circuit (I2C) Interface
12.1.2.1
I2C Overview
12.1.2.1.1
I2C Features
12.1.2.1.2
Integration
12.1.2.1.3
Unsupported Features
1740
12.1.2.2
I2C Environment
12.1.2.2.1
I2C Typical Application
12.1.2.2.1.1
I2C Pins for Typical Connections in I2C Mode
12.1.2.2.1.2
I2C Interface Typical Connections
12.1.2.2.1.3
1745
12.1.2.2.2
I2C Typical Connection Protocol and Data Format
12.1.2.2.2.1
I2C Serial Data Format
12.1.2.2.2.2
I2C Data Validity
12.1.2.2.2.3
I2C Start and Stop Conditions
12.1.2.2.2.4
I2C Addressing
12.1.2.2.2.4.1
Data Transfer Formats in F/S Mode
12.1.2.2.2.4.2
Data Transfer Format in HS Mode
12.1.2.2.2.5
I2C Controller Transmitter
12.1.2.2.2.6
I2C Controller Receiver
12.1.2.2.2.7
I2C Target Transmitter
12.1.2.2.2.8
I2C Target Receiver
12.1.2.2.2.9
I2C Bus Arbitration
12.1.2.2.2.10
I2C Clock Generation and Synchronization
12.1.2.3
I2C Functional Description
12.1.2.3.1
I2C Block Diagram
12.1.2.3.2
I2C Clocks
12.1.2.3.2.1
I2C Clocking
12.1.2.3.2.2
I2C Automatic Blocking of the I2C Clock Feature
12.1.2.3.3
I2C Software Reset
12.1.2.3.4
I2C Power Management
12.1.2.3.5
I2C Interrupt Requests
12.1.2.3.6
I2C Programmable Multitarget Channel Feature
12.1.2.3.7
I2C FIFO Management
12.1.2.3.7.1
I2C FIFO Interrupt Mode
12.1.2.3.7.2
I2C FIFO Polling Mode
12.1.2.3.7.3
I2C Draining Feature
12.1.2.3.8
I2C Noise Filter
12.1.2.3.9
I2C System Test Mode
12.1.2.4
I2C Programming Guide
12.1.2.4.1
I2C Low-Level Programming Models
12.1.2.4.1.1
I2C Programming Model
12.1.2.4.1.1.1
Main Program
12.1.2.4.1.1.1.1
Configure the Module Before Enabling the I2C Controller
12.1.2.4.1.1.1.2
Initialize the I2C Controller
12.1.2.4.1.1.1.3
Configure Target Address and the Data Control Register
12.1.2.4.1.1.1.4
Initiate a Transfer
12.1.2.4.1.1.1.5
Receive Data
12.1.2.4.1.1.1.6
Transmit Data
12.1.2.4.1.1.2
Interrupt Subroutine Sequence
12.1.2.4.1.1.3
Programming Flow-Diagrams
12.1.3
Multichannel Serial Peripheral Interface (MCSPI)
12.1.3.1
MCSPI Overview
12.1.3.1.1
MCSPI Features
12.1.3.1.2
Unsupported Features
1790
12.1.3.2
MCSPI Environment
12.1.3.2.1
Basic MCSPI Pins for Controller Mode
12.1.3.2.2
Basic MCSPI Pins for Peripheral Mode
12.1.3.2.3
MCSPI Protocol and Data Format
12.1.3.2.3.1
Transfer Format
12.1.3.2.4
MCSPI in Controller Mode
12.1.3.2.5
MCSPI in Peripheral Mode
12.1.3.3
Integration
12.1.3.4
MCSPI Functional Description
12.1.3.4.1
MCSPI Block Diagram
12.1.3.4.2
MCSPI Reset
12.1.3.4.3
MCSPI Controller Mode
12.1.3.4.3.1
Controller Mode Features
12.1.3.4.3.2
Controller Transmit-and-Receive Mode (Full Duplex)
12.1.3.4.3.3
Controller Transmit-Only Mode (Half Duplex)
12.1.3.4.3.4
Controller Receive-Only Mode (Half Duplex)
12.1.3.4.3.5
Single-Channel Controller Mode
12.1.3.4.3.5.1
Programming Tips When Switching to Another Channel
12.1.3.4.3.5.2
Force SPIEN_[n] Mode
12.1.3.4.3.5.3
Turbo Mode
12.1.3.4.3.6
Start-Bit Mode
12.1.3.4.3.7
Chip-Select Timing Control
12.1.3.4.3.8
Programmable MCSPI Clock (SPICLK)
12.1.3.4.3.8.1
Clock Ratio Granularity
12.1.3.4.4
MCSPI Peripheral Mode
12.1.3.4.4.1
Dedicated Resources
12.1.3.4.4.2
Peripheral Transmit-and-Receive Mode
12.1.3.4.4.3
Peripheral Transmit-Only Mode
12.1.3.4.4.4
Peripheral Receive-Only Mode
12.1.3.4.5
MCSPI 3-Pin or 4-Pin Mode
12.1.3.4.6
MCSPI FIFO Buffer Management
12.1.3.4.6.1
Buffer Almost Full
12.1.3.4.6.2
Buffer Almost Empty
12.1.3.4.6.3
End of Transfer Management
12.1.3.4.6.4
Multiple MCSPI Word Access
12.1.3.4.6.5
First MCSPI Word Delay
12.1.3.4.7
MCSPI Interrupts
12.1.3.4.7.1
Interrupt Events in Controller Mode
12.1.3.4.7.1.1
TXx_EMPTY
12.1.3.4.7.1.2
TXx_UNDERFLOW
12.1.3.4.7.1.3
RXx_ FULL
12.1.3.4.7.1.4
End Of Word Count
12.1.3.4.7.2
Interrupt Events in Peripheral Mode
12.1.3.4.7.2.1
TXx_EMPTY
12.1.3.4.7.2.2
TXx_UNDERFLOW
12.1.3.4.7.2.3
RXx_FULL
12.1.3.4.7.2.4
RX0_OVERFLOW
12.1.3.4.7.2.5
End Of Word Count
12.1.3.4.7.3
Interrupt-Driven Operation
12.1.3.4.7.4
Polling
12.1.3.4.8
MCSPI DMA Requests
12.1.3.4.9
MCSPI Power Saving Management
12.1.3.4.9.1
Normal Mode
12.1.3.4.9.2
Idle Mode
12.1.3.4.9.2.1
Force-Idle Mode
12.1.3.5
MCSPI Programming Guide
12.1.3.5.1
MCSPI Global Initialization
12.1.3.5.1.1
Surrounding Modules Global Initialization
12.1.3.5.1.2
MCSPI Global Initialization
12.1.3.5.1.2.1
Main Sequence – MCSPI Global Initialization
12.1.3.5.2
MCSPI Operational Mode Configuration
12.1.3.5.2.1
MCSPI Operational Modes
12.1.3.5.2.1.1
Common Transfer Sequence
12.1.3.5.2.1.2
End of Transfer Sequences
12.1.3.5.2.1.3
Transmit-and-Receive (Controller and Peripheral)
12.1.3.5.2.1.4
Transmit-Only (Controller and Peripheral)
12.1.3.5.2.1.4.1
Based on Interrupt Requests
12.1.3.5.2.1.4.2
Based on DMA Write Requests
12.1.3.5.2.1.5
Controller Normal Receive-Only
12.1.3.5.2.1.5.1
Based on Interrupt Requests
12.1.3.5.2.1.5.2
Based on DMA Read Requests
12.1.3.5.2.1.6
Controller Turbo Receive-Only
12.1.3.5.2.1.6.1
Based on Interrupt Requests
12.1.3.5.2.1.6.2
Based on DMA Read Requests
12.1.3.5.2.1.7
Peripheral Receive-Only
12.1.3.5.2.1.8
Transfer Procedures With FIFO
12.1.3.5.2.1.8.1
Common Transfer Sequence in FIFO Mode
12.1.3.5.2.1.8.2
End of Transfer Sequences in FIFO Mode
12.1.3.5.2.1.8.3
Transmit-and-Receive With Word Count
12.1.3.5.2.1.8.4
Transmit-and-Receive Without Word Count
12.1.3.5.2.1.8.5
Transmit-Only
12.1.3.5.2.1.8.6
Receive-Only With Word Count
12.1.3.5.2.1.8.7
Receive-Only Without Word Count
12.1.3.5.2.1.9
Common Transfer Procedures Without FIFO – Polling Method
12.1.3.5.2.1.9.1
Receive-Only Procedure – Polling Method
12.1.3.5.2.1.9.2
Receive-Only Procedure – Interrupt Method
12.1.3.5.2.1.9.3
Transmit-Only Procedure – Polling Method
12.1.3.5.2.1.9.4
Transmit-and-Receive Procedure – Polling Method
12.1.3.5.3
Common Transfer Procedures Without FIFO – Polling Method
12.1.3.5.3.1
Receive-Only Procedure – Polling Method
12.1.3.5.3.2
Receive-Only Procedure – Interrupt Method
12.1.3.5.3.3
Transmit-Only Procedure – Polling Method
12.1.3.5.3.4
Transmit-and-Receive Procedure – Polling Method
12.1.4
Universal Asynchronous Receiver/Transmitter (UART)
12.1.4.1
UART Overview
12.1.4.1.1
UART Features
12.1.4.1.2
Unsupported Features
1888
12.1.4.1.3
IrDA Features
12.1.4.1.4
CIR Features
12.1.4.2
UART Environment
12.1.4.2.1
UART Functional Interfaces
12.1.4.2.1.1
System Using UART Communication With Hardware Handshake
12.1.4.2.1.2
UART Interface Description
12.1.4.2.1.3
UART Protocol and Data Format
12.1.4.2.2
RS-485 Functional Interfaces
12.1.4.2.2.1
System Using RS-485 Communication
12.1.4.2.2.2
RS-485 Interface Description
12.1.4.2.3
IrDA Functional Interfaces
12.1.4.2.3.1
System Using IrDA Communication Protocol
12.1.4.2.3.2
IrDA Interface Description
12.1.4.2.3.3
IrDA Protocol and Data Format
12.1.4.2.3.3.1
SIR Mode
12.1.4.2.3.3.1.1
Frame Format
12.1.4.2.3.3.1.2
Asynchronous Transparency
12.1.4.2.3.3.1.3
Abort Sequence
12.1.4.2.3.3.1.4
Pulse Shaping
12.1.4.2.3.3.1.5
Encoder
12.1.4.2.3.3.1.6
Decoder
12.1.4.2.3.3.1.7
IR Address Checking
12.1.4.2.3.3.2
SIR Free-Format Mode
12.1.4.2.3.3.3
MIR Mode
12.1.4.2.3.3.3.1
MIR Encoder/Decoder
12.1.4.2.3.3.3.2
SIP Generation
12.1.4.2.3.3.4
FIR Mode
12.1.4.2.4
CIR Functional Interfaces
12.1.4.2.4.1
System Using CIR Communication Protocol With Remote Control
12.1.4.2.4.2
CIR Interface Description
12.1.4.2.4.3
CIR Protocol and Data Format
12.1.4.2.4.3.1
Carrier Modulation
12.1.4.2.4.3.2
Pulse Duty Cycle
12.1.4.2.4.3.3
Consumer IR Encoding/Decoding
12.1.4.3
Integration
12.1.4.4
UART Functional Description
12.1.4.4.1
UART Block Diagram
12.1.4.4.2
UART Clock Configuration
12.1.4.4.3
UART Software Reset
12.1.4.4.3.1
Independent TX/RX
12.1.4.4.4
UART Power Management
12.1.4.4.4.1
UART Mode Power Management
12.1.4.4.4.1.1
Module Power Saving
12.1.4.4.4.1.2
System Power Saving
12.1.4.4.4.2
IrDA Mode Power Management
12.1.4.4.4.2.1
Module Power Saving
12.1.4.4.4.2.2
System Power Saving
12.1.4.4.4.3
CIR Mode Power Management
12.1.4.4.4.3.1
Module Power Saving
12.1.4.4.4.3.2
System Power Saving
12.1.4.4.4.4
Local Power Management
12.1.4.4.5
UART Interrupt Requests
12.1.4.4.5.1
UART Mode Interrupt Management
12.1.4.4.5.1.1
UART Interrupts
12.1.4.4.5.1.2
Wake-Up Interrupt
12.1.4.4.5.2
IrDA Mode Interrupt Management
12.1.4.4.5.2.1
IrDA Interrupts
12.1.4.4.5.2.2
Wake-Up Interrupts
12.1.4.4.5.3
CIR Mode Interrupt Management
12.1.4.4.5.3.1
CIR Interrupts
12.1.4.4.5.3.2
Wake-Up Interrupts
12.1.4.4.6
UART FIFO Management
12.1.4.4.6.1
FIFO Trigger
12.1.4.4.6.1.1
Transmit FIFO Trigger
12.1.4.4.6.1.2
Receive FIFO Trigger
12.1.4.4.6.2
FIFO Interrupt Mode
12.1.4.4.6.3
FIFO Polled Mode Operation
12.1.4.4.6.4
FIFO DMA Mode Operation
12.1.4.4.6.4.1
DMA sequence to disable TX DMA
12.1.4.4.6.4.2
DMA Transfers (DMA Mode 1, 2, or 3)
12.1.4.4.6.4.3
DMA Transmission
12.1.4.4.6.4.4
DMA Reception
12.1.4.4.7
UART Mode Selection
12.1.4.4.7.1
Register Access Modes
12.1.4.4.7.1.1
Operational Mode and Configuration Modes
12.1.4.4.7.1.2
Register Access Submode
12.1.4.4.7.1.3
Registers Available for the Register Access Modes
12.1.4.4.7.2
UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
12.1.4.4.7.2.1
Registers Available for the UART Function
12.1.4.4.7.2.2
Registers Available for the IrDA Function
12.1.4.4.7.2.3
Registers Available for the CIR Function
12.1.4.4.8
UART Protocol Formatting
12.1.4.4.8.1
UART Mode
12.1.4.4.8.1.1
UART Clock Generation: Baud Rate Generation
12.1.4.4.8.1.2
Choosing the Appropriate Divisor Value
12.1.4.4.8.1.3
UART Data Formatting
12.1.4.4.8.1.3.1
Frame Formatting
12.1.4.4.8.1.3.2
Hardware Flow Control
12.1.4.4.8.1.3.3
Software Flow Control
1.4.4.8.1.3.3.1
Receive (RX)
1.4.4.8.1.3.3.2
Transmit (TX)
12.1.4.4.8.1.3.4
Autobauding Modes
12.1.4.4.8.1.3.5
Error Detection
12.1.4.4.8.1.3.6
Overrun During Receive
12.1.4.4.8.1.3.7
Time-Out and Break Conditions
1.4.4.8.1.3.7.1
Time-Out Counter
1.4.4.8.1.3.7.2
Break Condition
12.1.4.4.8.2
RS-485 Mode
12.1.4.4.8.2.1
RS-485 External Transceiver Direction Control
12.1.4.4.8.3
IrDA Mode
12.1.4.4.8.3.1
IrDA Clock Generation: Baud Generator
12.1.4.4.8.3.2
Choosing the Appropriate Divisor Value
12.1.4.4.8.3.3
IrDA Data Formatting
12.1.4.4.8.3.3.1
IR RX Polarity Control
12.1.4.4.8.3.3.2
IrDA Reception Control
12.1.4.4.8.3.3.3
IR Address Checking
12.1.4.4.8.3.3.4
Frame Closing
12.1.4.4.8.3.3.5
Store and Controlled Transmission
12.1.4.4.8.3.3.6
Error Detection
12.1.4.4.8.3.3.7
Underrun During Transmission
12.1.4.4.8.3.3.8
Overrun During Receive
12.1.4.4.8.3.3.9
Status FIFO
12.1.4.4.8.3.3.10
Multi-drop Parity Mode with Address Match
12.1.4.4.8.3.3.11
Time-guard
12.1.4.4.8.3.4
SIR Mode Data Formatting
12.1.4.4.8.3.4.1
Abort Sequence
12.1.4.4.8.3.4.2
Pulse Shaping
12.1.4.4.8.3.4.3
SIR Free Format Programming
12.1.4.4.8.3.5
MIR and FIR Mode Data Formatting
12.1.4.4.8.4
CIR Mode
12.1.4.4.8.4.1
CIR Mode Clock Generation
12.1.4.4.8.4.2
CIR Data Formatting
12.1.4.4.8.4.2.1
IR RX Polarity Control
12.1.4.4.8.4.2.2
CIR Transmission
12.1.4.4.8.4.2.3
CIR Reception
12.1.4.5
UART Programming Guide
12.1.4.5.1
UART Global Initialization
12.1.4.5.1.1
Surrounding Modules Global Initialization
12.1.4.5.1.2
UART Module Global Initialization
12.1.4.5.2
UART Mode selection
12.1.4.5.3
UART Submode selection
12.1.4.5.4
UART Load FIFO trigger and DMA mode settings
12.1.4.5.4.1
DMA mode Settings
12.1.4.5.4.2
FIFO Trigger Settings
12.1.4.5.5
UART Protocol, Baud rate and interrupt settings
12.1.4.5.5.1
Baud rate settings
12.1.4.5.5.2
Interrupt settings
12.1.4.5.5.3
Protocol settings
12.1.4.5.5.4
UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
12.1.4.5.5.5
UART Multi-drop Parity Address Match Mode Configuration
12.1.4.5.6
UART Hardware and Software Flow Control Configuration
12.1.4.5.6.1
Hardware Flow Control Configuration
12.1.4.5.6.2
Software Flow Control Configuration
12.1.4.5.7
IrDA Programming Model
12.1.4.5.7.1
SIR mode
12.1.4.5.7.1.1
Receive
12.1.4.5.7.1.2
Transmit
12.1.4.5.7.2
MIR mode
12.1.4.5.7.2.1
Receive
12.1.4.5.7.2.2
Transmit
12.1.4.5.7.3
FIR mode
12.1.4.5.7.3.1
Receive
12.1.4.5.7.3.2
Transmit
12.2
High-speed Serial Interfaces
12.2.1
Peripheral Component Interconnect Express (PCIe) Subsystem
12.2.1.1
PCIe Subsystem Overview
12.2.1.1.1
PCIe Subsystem Features
12.2.1.1.2
PCIe Subsystem Not Supported Features
12.2.1.2
PCIe Subsystem Environment
12.2.1.3
PCIe Subsystem Functional Description
12.2.1.3.1
PCIe Subsystem Block Diagram
12.2.1.3.1.1
PCIe PHY Interface
12.2.1.3.1.1.1
PCIe Core Module
12.2.1.3.1.2
Custom Logic
12.2.1.3.2
PCIe Subsystem Reset Schemes
12.2.1.3.2.1
PCIe Conventional Reset
12.2.1.3.2.2
PCIe Function Level Reset
12.2.1.3.2.3
PCIe Reset Isolation
12.2.1.3.2.3.1
Root Complex Reset with Device Not Reset
12.2.1.3.2.3.2
Device Reset with Root Complex Not Reset
12.2.1.3.2.3.3
End Point Device Reset with Root Complex Not Reset
12.2.1.3.2.3.4
Device Reset with End Point Device Not Reset
12.2.1.3.2.4
PCIe Reset Limitations
12.2.1.3.2.5
PCIe Reset Requirements
12.2.1.3.3
PCIe Subsystem Power Management
12.2.1.3.3.1
CBA Power Management
12.2.1.3.4
PCIe Subsystem Interrupts
12.2.1.3.4.1
Interrupts Aggregation
12.2.1.3.4.2
Interrupt Generation in EP Mode
12.2.1.3.4.2.1
Legacy Interrupt Generation in EP Mode
12.2.1.3.4.2.2
MSI and MSI-X Interrupt Generation
12.2.1.3.4.3
Interrupt Reception in EP Mode
12.2.1.3.4.3.1
PCIe Core Downstream Interrupts
12.2.1.3.4.3.2
PCIe Core Function Level Reset Interrupts
12.2.1.3.4.3.3
PCIe Core Power Management Event Interrupts
12.2.1.3.4.3.4
PCIe Core Hot Reset Request Interrupt
12.2.1.3.4.3.5
PTM Valid Interrupt
12.2.1.3.4.4
Interrupt Generation in RC Mode
12.2.1.3.4.5
Interrupt Reception in RC Mode
12.2.1.3.4.5.1
PCIe Legacy Interrupt Reception in RC Mode
12.2.1.3.4.5.2
MSI/MSI-X Interrupt Reception in RC Mode
12.2.1.3.4.5.3
Advanced Error Reporting Interrupt
12.2.1.3.4.6
Common Interrupt Reception in RC and EP Modes
12.2.1.3.4.6.1
PCIe Local Interrupt
12.2.1.3.4.6.2
PHY Interrupt
12.2.1.3.4.6.3
Link down Interrupt
12.2.1.3.4.6.4
Transaction Error Interrupts
12.2.1.3.4.6.5
Power Management Event Interrupt
12.2.1.3.4.7
ECC Aggregator Interrupts
12.2.1.3.4.8
CPTS Interrupt
12.2.1.3.5
PCIe Subsystem DMA Support
12.2.1.3.5.1
PCIe DMA Support in RC Mode
12.2.1.3.5.2
PCIe DMA Support in EP Mode
12.2.1.3.6
PCIe Subsystem Transactions
12.2.1.3.6.1
PCIe Supported Transactions
12.2.1.3.6.2
PCIe Transaction Limitations
12.2.1.3.7
PCIe Subsystem Address Translation
12.2.1.3.7.1
PCIe Inbound Address Translation
12.2.1.3.7.1.1
Root Complex Inbound PCIe to AXI Address Translation
12.2.1.3.7.1.2
End Point Inbound PCIe to AXI Address Translation
12.2.1.3.7.2
PCIe Outbound Address Translation
12.2.1.3.7.2.1
PCIe Outbound Address Translation Bypass
12.2.1.3.8
PCIe Subsystem Quality-of-Service (QoS)
12.2.1.3.9
PCIe Subsystem Precision Time Measurement (PTM)
12.2.1.3.10
PCIe Subsystem Loopback
12.2.1.3.10.1
PCIe Loopback
12.2.1.3.10.1.1
PCIe Loopback Initiator Mode
12.2.1.3.10.1.2
PCIe Loopback Target Mode
12.2.1.3.11
PCIe Subsystem Error Handling
12.2.1.3.12
PCIe Subsystem Internal Diagnostics Features
12.2.1.3.12.1
ECC Aggregators
12.2.1.3.12.2
RAM ECC Inversion
12.2.2
Serializer/Deserializer (SerDes)
12.2.2.1
SerDes Overview
12.2.2.1.1
SerDes Features
12.2.2.1.2
Not Supported Features
12.2.2.1.3
Industry Standards Compatibility
12.2.2.2
SerDes Environment
12.2.2.2.1
SerDes I/Os
12.2.2.3
SerDes Functional Description
12.2.2.3.1
SerDes Block Diagram
12.2.3
Universal Serial Bus Subsystem (USBSS)
12.2.3.1
USB Overview
12.2.3.1.1
USB Features
12.2.3.1.2
Unsupported Features
12.2.3.2
USB Environment
12.2.3.2.1
USB Pin List
12.2.3.2.2
Typical Pin Connections of Device
12.2.3.3
Integration
12.2.3.4
Use Cases
12.2.3.4.1
USB Operational Mode Determination
12.2.3.4.2
VBUS Voltage Sourcing Control
12.2.3.4.3
VBUS Detection
12.2.3.4.4
Pull-up/Pull-down Resistors
12.2.4
Universal Serial Bus Subsystem (USBSS)
12.2.4.1
USB Overview
12.2.4.1.1
USB Features
12.2.4.1.2
USB Not Supported Features
12.2.4.1.3
USB Terminology
12.2.4.2
USB Environment
12.2.4.2.1
USB I/Os
12.2.4.2.2
USB Subsystem Application
12.2.4.2.3
VBUS Sense
12.2.4.3
USB Functional Description
12.2.4.3.1
USB Controller Reset
12.2.4.3.2
Overcurrent Detection
12.2.4.3.3
Top-Level Initialization Sequence
12.3
Memory Interfaces
12.3.1
Flash Subsystem (FSS)
12.3.1.1
FSS Overview
12.3.1.1.1
FSS Features
12.3.1.1.2
Unsupported Features
2151
12.3.1.2
FSS Environment
12.3.1.2.1
FSS Typical Application
12.3.1.3
Integration
12.3.1.4
FSS Functional Description
12.3.1.4.1
FSS Block Diagram
12.3.1.4.2
FSS Regions
12.3.1.4.2.1
FSS Regions Boot Size Configuration
12.3.1.4.3
FSS Memory Regions
12.3.1.5
FSS Programming Guide
12.3.1.5.1
FSS Initialization Sequence
12.3.1.5.2
FSS Power Up/Down Sequence
12.3.2
Octal Serial Peripheral Interface (OSPI)
12.3.2.1
OSPI Overview
12.3.2.1.1
OSPI Features
12.3.2.1.2
Unsupported Features
2167
12.3.2.2
OSPI Environment
12.3.2.3
Integration
12.3.2.4
OSPI Functional Description
12.3.2.4.1
OSPI Block Diagram
12.3.2.4.1.1
Data Target Interface
12.3.2.4.1.2
Configuration Target Interface
12.3.2.4.1.3
OSPI Clock Domains
12.3.2.4.2
OSPI Modes
12.3.2.4.2.1
Read Data Capture
12.3.2.4.2.1.1
Mechanisms of Data Capturing
12.3.2.4.2.1.2
Data Capturing Mechanism Using Taps
12.3.2.4.2.1.3
Data Capturing Mechanism Using PHY Module
12.3.2.4.2.1.4
External Pull Down on DQS
12.3.2.4.3
OSPI Power Management
12.3.2.4.4
Auto HW Polling
12.3.2.4.5
Flash Reset
12.3.2.4.6
OSPI Memory Regions
12.3.2.4.7
OSPI Interrupt Requests
12.3.2.4.8
OSPI Data Interface
12.3.2.4.8.1
Data Interface Address Remapping
12.3.2.4.8.2
Write Protection
12.3.2.4.8.3
Access Forwarding
12.3.2.4.9
OSPI Direct Access Controller (DAC)
12.3.2.4.10
OSPI Indirect Access Controller (INDAC)
12.3.2.4.10.1
Indirect Read Controller
12.3.2.4.10.1.1
Indirect Read Transfer Process
12.3.2.4.10.2
Indirect Write Controller
12.3.2.4.10.2.1
Indirect Write Transfer Process
12.3.2.4.10.3
Indirect Access Queuing
12.3.2.4.10.4
Consecutive Writes and Reads Using Indirect Transfers
12.3.2.4.10.5
Accessing the SRAM
12.3.2.4.11
OSPI Software-Triggered Instruction Generator (STIG)
12.3.2.4.11.1
Servicing a STIG Request
12.3.2.4.12
OSPI Arbitration Between Direct / Indirect Access Controller and STIG
12.3.2.4.13
OSPI Command Translation
12.3.2.4.14
Selecting the Flash Instruction Type
12.3.2.4.15
OSPI Data Interface
12.3.2.4.16
OSPI PHY Module
12.3.2.4.16.1
PHY Pipeline Mode
12.3.2.4.16.2
Read Data Capturing by the PHY Module
12.3.2.5
OSPI Programming Guide
12.3.2.5.1
Configuring the OSPI Controller for Use After Reset
12.3.2.5.2
Configuring the OSPI Controller for Optimal Use
12.3.2.5.3
Using the Flash Command Control Register (STIG Operation)
12.3.2.5.4
Using SPI Legacy Mode
12.3.2.5.5
Entering XIP Mode from POR
12.3.2.5.6
Entering XIP Mode Otherwise
12.3.2.5.7
Exiting XIP Mode
12.3.3
General-Purpose Memory Controller (GPMC)
12.3.3.1
GPMC Overview
12.3.3.1.1
GPMC Features
12.3.3.1.2
Unsupported Features
2220
12.3.3.2
GPMC Environment
12.3.3.2.1
GPMC Modes
12.3.3.2.2
GPMC I/O Signals
12.3.3.3
Integration
12.3.3.4
GPMC Functional Description
12.3.3.4.1
GPMC Block Diagram
12.3.3.4.2
GPMC Clock Configuration
12.3.3.4.3
GPMC Power Management
12.3.3.4.4
GPMC Interrupt Requests
12.3.3.4.5
GPMC Interconnect Port Interface
12.3.3.4.6
GPMC Address and Data Bus
12.3.3.4.6.1
GPMC I/O Configuration Setting
12.3.3.4.7
GPMC Address Decoder and Chip-Select Configuration
12.3.3.4.7.1
Chip-Select Base Address and Region Size
12.3.3.4.7.2
Access Protocol
12.3.3.4.7.2.1
Supported Devices
12.3.3.4.7.2.2
Access Size Adaptation and Device Width
12.3.3.4.7.2.3
Address/Data-Multiplexing Interface
12.3.3.4.7.3
External Signals
12.3.3.4.7.3.1
WAIT Pin Monitoring Control
12.3.3.4.7.3.1.1
Wait Monitoring During Asynchronous Read Access
12.3.3.4.7.3.1.2
Wait Monitoring During Asynchronous Write Access
12.3.3.4.7.3.1.3
Wait Monitoring During Synchronous Read Access
12.3.3.4.7.3.1.4
Wait Monitoring During Synchronous Write Access
12.3.3.4.7.3.1.5
Wait With NAND Device
12.3.3.4.7.3.1.6
Idle Cycle Control Between Successive Accesses
3.3.4.7.3.1.6.1
Bus Turnaround (BUSTURNAROUND)
3.3.4.7.3.1.6.2
Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
3.3.4.7.3.1.6.3
Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
12.3.3.4.7.3.1.7
Slow Device Support (TIMEPARAGRANULARITY Parameter)
12.3.3.4.7.3.2
DIR Pin
12.3.3.4.7.3.3
Reset
12.3.3.4.7.3.4
Write Protect Signal (nWP)
12.3.3.4.7.3.5
Byte Enable (nBE1/nBE0)
12.3.3.4.7.4
Error Handling
12.3.3.4.8
GPMC Timing Setting
12.3.3.4.8.1
Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
12.3.3.4.8.2
nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
12.3.3.4.8.3
nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
12.3.3.4.8.4
nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
12.3.3.4.8.5
nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
12.3.3.4.8.6
GPMC_CLKOUT
12.3.3.4.8.7
GPMC Output Clock and Control Signals Setup and Hold
12.3.3.4.8.8
Access Time (RDACCESSTIME / WRACCESSTIME)
12.3.3.4.8.8.1
Access Time on Read Access
12.3.3.4.8.8.2
Access Time on Write Access
12.3.3.4.8.9
Page Burst Access Time (PAGEBURSTACCESSTIME)
12.3.3.4.8.9.1
Page Burst Access Time on Read Access
12.3.3.4.8.9.2
Page Burst Access Time on Write Access
12.3.3.4.8.10
Bus Keeping Support
12.3.3.4.9
GPMC NOR Access Description
12.3.3.4.9.1
Asynchronous Access Description
12.3.3.4.9.1.1
Access on Address/Data Multiplexed Devices
12.3.3.4.9.1.1.1
Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
12.3.3.4.9.1.1.2
Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
12.3.3.4.9.1.1.3
Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
12.3.3.4.9.1.2
Access on Address/Address/Data-Multiplexed Devices
12.3.3.4.9.1.2.1
Asynchronous Single Read Operation on an AAD-Multiplexed Device
12.3.3.4.9.1.2.2
Asynchronous Single-Write Operation on an AAD-Multiplexed Device
12.3.3.4.9.1.2.3
Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
12.3.3.4.9.2
Synchronous Access Description
12.3.3.4.9.2.1
Synchronous Single Read
12.3.3.4.9.2.2
Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
12.3.3.4.9.2.3
Synchronous Single Write
12.3.3.4.9.2.4
Synchronous Multiple (Burst) Write
12.3.3.4.9.3
Asynchronous and Synchronous Accesses in non-multiplexed Mode
12.3.3.4.9.3.1
Asynchronous Single-Read Operation on non-multiplexed Device
12.3.3.4.9.3.2
Asynchronous Single-Write Operation on non-multiplexed Device
12.3.3.4.9.3.3
Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
12.3.3.4.9.3.4
Synchronous Operations on a non-multiplexed Device
12.3.3.4.9.4
Page and Burst Support
12.3.3.4.9.5
System Burst vs External Device Burst Support
12.3.3.4.10
GPMC pSRAM Access Specificities
12.3.3.4.11
GPMC NAND Access Description
12.3.3.4.11.1
NAND Memory Device in Byte or 16-bit Word Stream Mode
12.3.3.4.11.1.1
Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
12.3.3.4.11.1.2
NAND Device Command and Address Phase Control
12.3.3.4.11.1.3
Command Latch Cycle
12.3.3.4.11.1.4
Address Latch Cycle
12.3.3.4.11.1.5
NAND Device Data Read and Write Phase Control in Stream Mode
12.3.3.4.11.1.6
NAND Device General Chip-Select Timing Control Requirement
12.3.3.4.11.1.7
Read and Write Access Size Adaptation
12.3.3.4.11.1.7.1
8-Bit-Wide NAND Device
12.3.3.4.11.1.7.2
16-Bit-Wide NAND Device
12.3.3.4.11.2
NAND Device-Ready Pin
12.3.3.4.11.2.1
Ready Pin Monitored by Software Polling
12.3.3.4.11.2.2
Ready Pin Monitored by Hardware Interrupt
12.3.3.4.11.3
ECC Calculator
12.3.3.4.11.3.1
Hamming Code
12.3.3.4.11.3.1.1
ECC Result Register and ECC Computation Accumulation Size
12.3.3.4.11.3.1.2
ECC Enabling
12.3.3.4.11.3.1.3
ECC Computation
12.3.3.4.11.3.1.4
ECC Comparison and Correction
12.3.3.4.11.3.1.5
ECC Calculation Based on 8-Bit Word
12.3.3.4.11.3.1.6
ECC Calculation Based on 16-Bit Word
12.3.3.4.11.3.2
BCH Code
12.3.3.4.11.3.2.1
Requirements
12.3.3.4.11.3.2.2
Memory Mapping of BCH Codeword
3.3.4.11.3.2.2.1
Memory Mapping of Data Message
3.3.4.11.3.2.2.2
Memory-Mapping of the ECC
3.3.4.11.3.2.2.3
Wrapping Modes
3.4.11.3.2.2.3.1
Manual Mode (0x0)
3.4.11.3.2.2.3.2
Mode 0x1
3.4.11.3.2.2.3.3
Mode 0xA (10)
3.4.11.3.2.2.3.4
Mode 0x2
3.4.11.3.2.2.3.5
Mode 0x3
3.4.11.3.2.2.3.6
Mode 0x7
3.4.11.3.2.2.3.7
Mode 0x8
3.4.11.3.2.2.3.8
Mode 0x4
3.4.11.3.2.2.3.9
Mode 0x9
3.4.11.3.2.2.3.10
Mode 0x5
3.4.11.3.2.2.3.11
Mode 0xB (11)
3.4.11.3.2.2.3.12
Mode 0x6
12.3.3.4.11.3.2.3
Supported NAND Page Mappings and ECC Schemes
3.3.4.11.3.2.3.1
Per-Sector Spare Mappings
3.3.4.11.3.2.3.2
Pooled Spare Mapping
3.3.4.11.3.2.3.3
Per-Sector Spare Mapping, with ECC Separated at the End of the Page
12.3.3.4.11.4
Prefetch and Write-Posting Engine
12.3.3.4.11.4.1
General Facts About the Engine Configuration
12.3.3.4.11.4.2
Prefetch Mode
12.3.3.4.11.4.3
FIFO Control in Prefetch Mode
12.3.3.4.11.4.4
Write-Posting Mode
12.3.3.4.11.4.5
FIFO Control in Write-Posting Mode
12.3.3.4.11.4.6
Optimizing NAND Access Using the Prefetch and Write-Posting Engine
12.3.3.4.11.4.7
Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
12.3.3.4.12
GPMC Use Cases and Tips
12.3.3.4.12.1
How to Set GPMC Timing Parameters for Typical Accesses
12.3.3.4.12.1.1
External Memory Attached to the GPMC Module
12.3.3.4.12.1.2
Typical GPMC Setup
12.3.3.4.12.1.2.1
GPMC Configuration for Synchronous Burst Read Access
12.3.3.4.12.1.2.2
GPMC Configuration for Asynchronous Read Access
12.3.3.4.12.1.2.3
GPMC Configuration for Asynchronous Single Write Access
12.3.3.4.12.2
How to Choose a Suitable Memory to Use With the GPMC
12.3.3.4.12.2.1
Supported Memories or Devices
12.3.3.4.12.2.1.1
Memory Pin Multiplexing
12.3.3.4.12.2.1.2
NAND Interface Protocol
12.3.3.4.12.2.1.3
NOR Interface Protocol
12.3.3.4.12.2.1.4
Other Technologies
12.3.3.5
GPMC Basic Programming Model
12.3.3.5.1
GPMC High-Level Programming Model Overview
12.3.3.5.2
GPMC Initialization
12.3.3.5.3
GPMC Configuration in NOR Mode
12.3.3.5.4
GPMC Configuration in NAND Mode
12.3.3.5.5
Set Memory Access
12.3.3.5.6
GPMC Timing Parameters
12.3.3.5.6.1
GPMC Timing Parameters Formulas
12.3.3.5.6.1.1
NAND Flash Interface Timing Parameters Formulas
12.3.3.5.6.1.2
Synchronous NOR Flash Timing Parameters Formulas
12.3.3.5.6.1.3
Asynchronous NOR Flash Timing Parameters Formulas
12.3.4
Error Location Module (ELM)
12.3.4.1
ELM Overview
12.3.4.1.1
ELM Features
12.3.4.1.2
Unsupported Features
2374
12.3.4.2
Integration
12.3.4.3
ELM Functional Description
12.3.4.3.1
ELM Software Reset
12.3.4.3.2
ELM Power Management
12.3.4.3.3
ELM Interrupt Requests
12.3.4.3.4
ELM Processing Initialization
12.3.4.3.5
ELM Processing Sequence
12.3.4.3.6
ELM Processing Completion
12.3.4.4
ELM Basic Programming Model
12.3.4.4.1
ELM Low-Level Programming Model
12.3.4.4.1.1
Processing Initialization
12.3.4.4.1.2
Read Results
12.3.4.4.1.3
2387
12.3.4.4.2
Use Case: ELM Used in Continuous Mode
12.3.4.4.3
Use Case: ELM Used in Page Mode
12.3.5
Multi-Media Card Secure Digital (MMCSD) Interface
12.3.5.1
MMCSD Overview
12.3.5.1.1
MMCSD Features
12.3.5.1.2
Unsupported Features
2394
12.3.5.2
MMCSD Environment
12.3.5.2.1
MMCSD IO Mulitplexer
12.3.5.2.2
Protocol and Data Format
12.3.5.2.2.1
Protocol
12.3.5.2.2.2
Data Format
12.3.5.2.2.2.1
Coding Scheme for Command Token
12.3.5.2.2.2.2
Coding Scheme for Response Token
12.3.5.2.2.2.3
Coding Scheme for Data Token
12.3.5.3
Integration
12.3.5.4
MMCSD Functional Description
12.3.5.4.1
Block Diagram
12.3.5.4.2
Interrupt Requests
12.3.5.4.3
ECC Support
12.3.5.4.3.1
ECC Aggregator
12.3.5.4.4
Advanced DMA
12.3.5.5
MMCSD Programming Guide
12.3.5.5.1
Sequences
12.3.5.5.1.1
SD Card Detection
12.3.5.5.1.2
SD Clock Control
12.3.5.5.1.2.1
Internal Clock Setup Sequence
12.3.5.5.1.2.2
SD Clock Supply and Stop Sequence
12.3.5.5.1.2.3
SD Clock Frequency Change Sequence
12.3.5.5.1.3
SD Bus Power Control
12.3.5.5.1.4
Changing Bus Width
12.3.5.5.1.5
Timeout Setting on DAT Line
12.3.5.5.1.6
Card Initialization and Identification (for SD I/F)
12.3.5.5.1.6.1
Signal Voltage Switch Procedure (for UHS-I)
12.3.5.5.1.7
SD Transaction Generation
12.3.5.5.1.7.1
Transaction Control without Data Transfer Using DAT Line
12.3.5.5.1.7.1.1
The Sequence to Issue a SD Command
12.3.5.5.1.7.1.2
The Sequence to Finalize a Command
12.3.5.5.1.7.1.3
2426
12.3.5.5.1.7.2
Transaction Control with Data Transfer Using DAT Line
12.3.5.5.1.7.2.1
Not using DMA
12.3.5.5.1.7.2.2
Using SDMA
12.3.5.5.1.7.2.3
Using ADMA
12.3.5.5.1.8
Abort Transaction
12.3.5.5.1.8.1
Asynchronous Abort
12.3.5.5.1.8.2
Synchronous Abort
12.3.5.5.1.9
Changing Bus Speed Mode
12.3.5.5.1.10
Error Recovery
12.3.5.5.1.10.1
Error Interrupt Recovery
12.3.5.5.1.10.2
Auto CMD12 Error Recovery
12.3.5.5.1.11
Wakeup Control (Optional)
12.3.5.5.1.12
Suspend/Resume (Optional, Not Supported from Version 4.00)
12.3.5.5.1.12.1
Suspend Sequence
12.3.5.5.1.12.2
Resume Sequence
12.3.5.5.1.12.3
Stop At Block Gap/Continue Timing for Read Transaction
12.3.5.5.1.12.4
Stop At Block Gap/Continue Timing for Write Transaction
12.3.5.5.2
Driver Flow Sequence
12.3.5.5.2.1
Host Controller Setup and Card Detection
12.3.5.5.2.1.1
Host Controller Setup Sequence
12.3.5.5.2.1.2
Card Interface Detection Sequence
12.3.5.5.2.2
Boot Operation
12.3.5.5.2.2.1
Normal Boot Operation: (For Legacy eMMC 5.0)
12.3.5.5.2.2.2
Alternate Boot Operation (For Legacy eMMC 5.0):
12.3.5.5.2.2.3
Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
12.3.5.5.2.3
Retuning procedure (For Legacy Interface)
12.3.5.5.2.3.1
Sampling Clock Tuning
12.3.5.5.2.3.2
Tuning Sequence
12.3.5.5.2.3.3
Re-Tuning Modes
12.3.5.5.2.4
Command Queuing Driver Flow Sequence
12.3.5.5.2.4.1
Command Queuing Initialization Sequence
12.3.5.5.2.4.2
Task Issuance Sequence
12.3.5.5.2.4.3
Task Execution and Completion Sequence
12.3.5.5.2.4.4
Task Discard and Clear Sequence
12.3.5.5.2.4.5
Error Detect and Recovery when CQ is enabled
12.4
Industrial and Communication Interfaces
12.4.1
Modular Controller Area Network (MCAN)
12.4.1.1
MCAN Overview
12.4.1.1.1
MCAN Features
12.4.1.1.2
Unsupported Features
2467
12.4.1.2
MCAN Environment
12.4.1.2.1
CAN Network Basics
12.4.1.3
Integration
12.4.1.4
MCAN Functional Description
12.4.1.4.1
Module Clocking Requirements
12.4.1.4.2
Interrupt and DMA Requests
12.4.1.4.2.1
Interrupt Requests
12.4.1.4.2.2
DMA Requests
12.4.1.4.3
Operating Modes
12.4.1.4.3.1
Software Initialization
12.4.1.4.3.2
Normal Operation
12.4.1.4.3.3
CAN FD Operation
12.4.1.4.3.4
Transmitter Delay Compensation
12.4.1.4.3.4.1
Description
12.4.1.4.3.4.2
Transmitter Delay Compensation Measurement
12.4.1.4.3.5
Restricted Operation Mode
12.4.1.4.3.6
Bus Monitoring Mode
12.4.1.4.3.7
Disabled Automatic Retransmission (DAR) Mode
12.4.1.4.3.7.1
Frame Transmission in DAR Mode
12.4.1.4.3.8
Power Down (Sleep Mode)
12.4.1.4.3.8.1
External Clock Stop Mode
12.4.1.4.3.8.2
Suspend Mode
12.4.1.4.3.8.3
Wakeup request
12.4.1.4.3.9
Test Modes
12.4.1.4.3.9.1
Internal Loopback Mode
12.4.1.4.4
Timestamp Generation
12.4.1.4.4.1
External Timestamp Counter
12.4.1.4.5
Timeout Counter
12.4.1.4.6
ECC Support
12.4.1.4.6.1
ECC Wrapper
12.4.1.4.6.2
ECC Aggregator
12.4.1.4.7
Rx Handling
12.4.1.4.7.1
Acceptance Filtering
12.4.1.4.7.1.1
Range Filter
12.4.1.4.7.1.2
Filter for specific IDs
12.4.1.4.7.1.3
Classic Bit Mask Filter
12.4.1.4.7.1.4
Standard Message ID Filtering
12.4.1.4.7.1.5
Extended Message ID Filtering
12.4.1.4.7.2
Rx FIFOs
12.4.1.4.7.2.1
Rx FIFO Blocking Mode
12.4.1.4.7.2.2
Rx FIFO Overwrite Mode
12.4.1.4.7.3
Dedicated Rx Buffers
12.4.1.4.7.3.1
Rx Buffer Handling
12.4.1.4.7.4
Debug on CAN Support
12.4.1.4.8
Tx Handling
12.4.1.4.8.1
Transmit Pause
12.4.1.4.8.2
Dedicated Tx Buffers
12.4.1.4.8.3
Tx FIFO
12.4.1.4.8.4
Tx Queue
12.4.1.4.8.5
Mixed Dedicated Tx Buffers/Tx FIFO
12.4.1.4.8.6
Mixed Dedicated Tx Buffers/Tx Queue
12.4.1.4.8.7
Transmit Cancellation
12.4.1.4.8.8
Tx Event Handling
12.4.1.4.9
FIFO Acknowledge Handling
12.4.1.4.10
Message RAM
12.4.1.4.10.1
Message RAM Configuration
12.4.1.4.10.2
Rx Buffer and FIFO Element
12.4.1.4.10.3
Tx Buffer Element
12.4.1.4.10.4
Tx Event FIFO Element
12.4.1.4.10.5
Standard Message ID Filter Element
12.4.1.4.10.6
Extended Message ID Filter Element
12.4.2
Enhanced Capture (ECAP) Module
12.4.2.1
ECAP Overview
12.4.2.1.1
ECAP Features
12.4.2.1.2
Unsupported Features
2533
12.4.2.2
ECAP Environment
12.4.2.2.1
ECAP I/O Interface
12.4.2.3
Integration
12.4.2.4
ECAP Functional Description
12.4.2.4.1
Capture and APWM Operating Modes
12.4.2.4.1.1
ECAP Capture Mode Description
12.4.2.4.1.1.1
ECAP Event Prescaler
12.4.2.4.1.1.2
ECAP Edge Polarity Select and Qualifier
12.4.2.4.1.1.3
ECAP Continuous/One-Shot Control
12.4.2.4.1.1.4
ECAP 32-Bit Counter and Phase Control
12.4.2.4.1.1.5
CAP1-CAP4 Registers
12.4.2.4.1.1.6
ECAP Interrupt Control
12.4.2.4.1.1.7
ECAP Shadow Load and Lockout Control
12.4.2.4.1.2
ECAP APWM Mode Operation
12.4.2.4.2
Summary of ECAP Functional Registers
12.4.2.5
ECAP Use Cases
12.4.2.5.1
Absolute Time-Stamp Operation Rising Edge Trigger Example
12.4.2.5.1.1
Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
12.4.2.5.2
Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
12.4.2.5.2.1
Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
12.4.2.5.3
Time Difference (Delta) Operation Rising Edge Trigger Example
12.4.2.5.3.1
Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
12.4.2.5.4
Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
12.4.2.5.4.1
Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
12.4.2.5.5
Application of the APWM Mode
12.4.2.5.5.1
Simple PWM Generation (Independent Channel/s) Example
12.4.2.5.5.1.1
Code Snippet for APWM Mode
12.4.2.5.5.2
Multichannel PWM Generation with Synchronization Example
12.4.2.5.5.2.1
Code Snippet for Multichannel PWM Generation with Synchronization
12.4.2.5.5.3
Multichannel PWM Generation with Phase Control Example
12.4.2.5.5.3.1
Code Snippet for Multichannel PWM Generation with Phase Control
12.4.3
Enhanced Pulse Width Modulation (EPWM) Module
12.4.3.1
EPWM Overview
12.4.3.1.1
EPWM Features
12.4.3.1.2
Unsupported Features
2569
12.4.3.1.3
Multiple EPWM Module Details
12.4.3.2
EPWM Environment
12.4.3.3
Integration
12.4.3.4
EPWM Functional Description
12.4.3.4.1
EPWM Submodule Features
12.4.3.4.1.1
Constant Definitions Used in the EPWM Code Examples
12.4.3.4.2
EPWM Time-Base (TB) Submodule
12.4.3.4.2.1
Overview
12.4.3.4.2.2
Controlling and Monitoring the EPWM Time-Base Submodule
12.4.3.4.2.3
Calculating PWM Period and Frequency
12.4.3.4.2.3.1
EPWM Time-Base Period Shadow Register
12.4.3.4.2.3.2
EPWM Time-Base Counter Synchronization
12.4.3.4.2.4
Phase Locking the Time-Base Clocks of Multiple EPWM Modules
12.4.3.4.2.5
EPWM Time-Base Counter Modes and Timing Waveforms
12.4.3.4.3
EPWM Counter-Compare (CC) Submodule
12.4.3.4.3.1
Overview
12.4.3.4.3.2
Controlling and Monitoring the EPWM Counter-Compare Submodule
12.4.3.4.3.3
Operational Highlights for the EPWM Counter-Compare Submodule
12.4.3.4.3.4
EPWM Counter-Compare Submodule Timing Waveforms
12.4.3.4.4
EPWM Action-Qualifier (AQ) Submodule
12.4.3.4.4.1
Overview
12.4.3.4.4.2
Controlling and Monitoring the EPWM Action-Qualifier Submodule
12.4.3.4.4.3
EPWM Action-Qualifier Event Priority
12.4.3.4.4.4
Waveforms for Common EPWM Configurations
12.4.3.4.5
EPWM Dead-Band Generator (DB) Submodule
12.4.3.4.5.1
Overview
12.4.3.4.5.2
Controlling and Monitoring the EPWM Dead-Band Submodule
12.4.3.4.5.3
Operational Highlights for the EPWM Dead-Band Generator Submodule
12.4.3.4.6
EPWM-Chopper (PC) Submodule
12.4.3.4.6.1
Overview
12.4.3.4.6.2
2600
12.4.3.4.6.3
Controlling the EPWM-Chopper Submodule
12.4.3.4.6.4
Operational Highlights for the EPWM-Chopper Submodule
12.4.3.4.6.5
EPWM-Chopper Waveforms
12.4.3.4.6.5.1
EPWM-Chopper One-Shot Pulse
12.4.3.4.6.5.2
EPWM-Chopper Duty Cycle Control
12.4.3.4.7
EPWM Trip-Zone (TZ) Submodule
12.4.3.4.7.1
Overview
12.4.3.4.7.2
Controlling and Monitoring the EPWM Trip-Zone Submodule
12.4.3.4.7.3
Operational Highlights for the EPWM Trip-Zone Submodule
12.4.3.4.7.4
Generating EPWM Trip-Event Interrupts
12.4.3.4.8
EPWM Event-Trigger (ET) Submodule
12.4.3.4.8.1
Overview
12.4.3.4.8.2
Controlling and Monitoring the EPWM Event-Trigger Submodule
12.4.3.4.8.3
Operational Overview of the EPWM Event-Trigger Submodule
12.4.3.4.8.4
Operation Overview of the EPWM SOCx Pulse Generator
12.4.3.4.9
EPWM Functional Register Groups
12.4.3.4.10
Proper EPWM Interrupt Initialization Procedure
12.4.4
Enhanced Quadrature Encoder Pulse (EQEP) Module
12.4.4.1
EQEP Overview
12.4.4.1.1
EQEP Features
12.4.4.1.2
Unsupported Features
2622
12.4.4.2
EQEP Environment
12.4.4.2.1
EQEP I/O Interface
12.4.4.3
Integration
12.4.4.4
EQEP Functional Description
12.4.4.4.1
EQEP Inputs
12.4.4.4.2
EQEP Quadrature Decoder Unit (QDU)
12.4.4.4.2.1
EQEP Position Counter Input Modes
12.4.4.4.2.1.1
Quadrature Count Mode
12.4.4.4.2.1.2
EQEP Direction-count Mode
12.4.4.4.2.1.3
EQEP Up-Count Mode
12.4.4.4.2.1.4
EQEP Down-Count Mode
12.4.4.4.2.2
EQEP Input Polarity Selection
12.4.4.4.2.3
EQEP Position-Compare Sync Output
12.4.4.4.3
EQEP Position Counter and Control Unit (PCCU)
12.4.4.4.3.1
EQEP Position Counter Operating Modes
12.4.4.4.3.1.1
EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
12.4.4.4.3.1.2
EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b01)
12.4.4.4.3.1.3
Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
12.4.4.4.3.1.4
Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
12.4.4.4.3.2
EQEP Position Counter Latch
12.4.4.4.3.2.1
Index Event Latch
12.4.4.4.3.2.2
EQEP Strobe Event Latch
12.4.4.4.3.3
EQEP Position Counter Initialization
12.4.4.4.3.4
EQEP Position-Compare Unit
12.4.4.4.4
EQEP Edge Capture Unit
12.4.4.4.5
EQEP Watchdog
12.4.4.4.6
Unit Timer Base
12.4.4.4.7
EQEP Interrupt Structure
12.4.4.4.8
Summary of EQEP Functional Registers
12.5
Audio Peripherals
12.5.1
Audio Tracking Logic (ATL)
12.5.1.1
ATL Overview
12.5.1.1.1
ATL Features Overview
12.5.1.1.2
ATL Ports
12.5.2
Multichannel Audio Serial Port (MCASP)
12.5.2.1
MCASP Overview
12.5.2.1.1
MCASP Features
2660
12.5.2.1.2
Unsupported Features
12.5.2.2
MCASP Environment
12.5.2.2.1
MCASP Signals
12.5.2.2.2
MCASP Protocols and Data Formats
12.5.2.2.2.1
Protocols Supported
12.5.2.2.2.2
Definition of Terms
12.5.2.2.2.3
TDM Format
12.5.2.2.2.4
I2S Format
12.5.2.2.2.5
S/PDIF Coding Format
12.5.2.2.2.5.1
Biphase-Mark Code
12.5.2.2.2.5.2
S/PDIF Subframe Format
12.5.2.2.2.5.3
Frame Format
12.5.2.3
Integration
12.5.2.4
MCASP Functional Description
12.5.2.4.1
MCASP Block Diagram
12.5.2.4.2
MCASP Clock and Frame-Sync Configurations
12.5.2.4.2.1
MCASP Transmit Clock
12.5.2.4.2.2
MCASP Receive Clock
12.5.2.4.2.3
Frame-Sync Generator
12.5.2.4.2.4
Synchronous and Asynchronous Transmit and Receive Operations
12.5.2.4.3
MCASP Serializers
12.5.2.4.4
MCASP Format Units
12.5.2.4.4.1
Transmit Format Unit
12.5.2.4.4.1.1
TDM Mode Transmission Data Alignment Settings
12.5.2.4.4.1.2
DIT Mode Transmission Data Alignment Settings
12.5.2.4.4.2
Receive Format Unit
12.5.2.4.4.2.1
TDM Mode Reception Data Alignment Settings
12.5.2.4.5
MCASP State-Machines
12.5.2.4.6
MCASP TDM Sequencers
12.5.2.4.7
MCASP Software Reset
12.5.2.4.8
MCASP Power Management
12.5.2.4.9
MCASP Transfer Modes
12.5.2.4.9.1
Burst Transfer Mode
12.5.2.4.9.2
Time-Division Multiplexed (TDM) Transfer Mode
12.5.2.4.9.2.1
TDM Time Slots Generation and Processing
12.5.2.4.9.2.2
Special 384-Slot TDM Mode for Connection to External DIR
12.5.2.4.9.3
DIT Transfer Mode
12.5.2.4.9.3.1
Transmit DIT Encoding
12.5.2.4.9.3.2
Transmit DIT Clock and Frame-Sync Generation
12.5.2.4.9.3.3
DIT Channel Status and User Data Register Files
12.5.2.4.10
MCASP Data Transmission and Reception
12.5.2.4.10.1
Data Ready Status and Event/Interrupt Generation
12.5.2.4.10.1.1
Transmit Data Ready
12.5.2.4.10.1.2
Receive Data Ready
12.5.2.4.10.1.3
Transfers Through the Data Port (DATA)
12.5.2.4.10.1.4
Transfers Through the Configuration Bus (CFG)
12.5.2.4.10.1.5
Using a Device CPU for MCASP Servicing
12.5.2.4.10.1.6
Using the DMA for MCASP Servicing
12.5.2.4.11
MCASP Audio FIFO (AFIFO)
12.5.2.4.11.1
AFIFO Data Transmission
12.5.2.4.11.1.1
Transmit DMA Event Pacer
12.5.2.4.11.2
AFIFO Data Reception
12.5.2.4.11.2.1
Receive DMA Event Pacer
12.5.2.4.11.3
Arbitration Between Transmit and Receive DMA Requests
12.5.2.4.12
MCASP Events and Interrupt Requests
12.5.2.4.12.1
Transmit Data Ready Event and Interrupt
12.5.2.4.12.2
Receive Data Ready Event and Interrupt
12.5.2.4.12.3
Error Interrupt
12.5.2.4.12.4
Multiple Interrupts
12.5.2.4.13
MCASP DMA Requests
12.5.2.4.14
MCASP Loopback Modes
12.5.2.4.14.1
Loopback Mode Configurations
12.5.2.4.15
MCASP Error Reporting
12.5.2.4.15.1
Buffer Underrun Error -Transmitter
12.5.2.4.15.2
Buffer Overrun Error-Receiver
12.5.2.4.15.3
DATA Port Error - Transmitter
12.5.2.4.15.4
DATA Port Error - Receiver
12.5.2.4.15.5
Unexpected Frame Sync Error
12.5.2.4.15.6
Clock Failure Detection
12.5.2.4.15.6.1
Clock Failure Check Startup
12.5.2.4.15.6.2
Transmit Clock Failure Check and Recovery
12.5.2.4.15.6.3
Receive Clock Failure Check and Recovery
12.5.2.5
MCASP Programming Guide
12.5.2.5.1
MCASP Global Initialization
12.5.2.5.1.1
Surrounding Modules Global Initialization
12.5.2.5.1.2
MCASP Global Initialization
12.5.2.5.1.2.1
Main Sequence – MCASP Global Initialization for DIT-Transmission
12.5.2.5.1.2.1.1
Subsequence – Transmit Format Unit Configuration for DIT-Transmission
12.5.2.5.1.2.1.2
Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
12.5.2.5.1.2.1.3
Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
12.5.2.5.1.2.1.4
Subsequence - MCASP Pins Functional Configuration
12.5.2.5.1.2.1.5
Subsequence – DIT-specific Subframe Fields Configuration
12.5.2.5.1.2.2
Main Sequence – MCASP Global Initialization for TDM-Reception
12.5.2.5.1.2.2.1
Subsequence – Receive Format Unit Configuration in TDM Mode
12.5.2.5.1.2.2.2
Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
12.5.2.5.1.2.2.3
Subsequence – Receive Clock Generator Configuration
12.5.2.5.1.2.2.4
Subsequence—MCASP Receiver Pins Functional Configuration
12.5.2.5.1.2.3
Main Sequence – MCASP Global Initialization for TDM -Transmission
12.5.2.5.1.2.3.1
Subsequence – Transmit Format Unit Configuration in TDM Mode
12.5.2.5.1.2.3.2
Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
12.5.2.5.1.2.3.3
Subsequence – Transmit Clock Generator Configuration for TDM Cases
12.5.2.5.1.2.3.4
Subsequence—MCASP Transmit Pins Functional Configuration
12.5.2.5.2
MCASP Operational Modes Configuration
12.5.2.5.2.1
MCASP Transmission Modes
12.5.2.5.2.1.1
Main Sequence – MCASP DIT- /TDM- Polling Transmission Method
12.5.2.5.2.1.2
Main Sequence – MCASP DIT- /TDM - Interrupt Transmission Method
12.5.2.5.2.1.3
Main Sequence –MCASP DIT- /TDM - Mode DMA Transmission Method
12.5.2.5.2.2
MCASP Reception Modes
12.5.2.5.2.2.1
Main Sequence – MCASP Polling Reception Method
12.5.2.5.2.2.2
Main Sequence – MCASP TDM - Interrupt Reception Method
12.5.2.5.2.2.3
Main Sequence – MCASP TDM - Mode DMA Reception Method
12.5.2.5.2.3
MCASP Event Servicing
12.5.2.5.2.3.1
MCASP DIT-/TDM- Transmit Interrupt Events Servicing
12.5.2.5.2.3.2
MCASP TDM- Receive Interrupt Events Servicing
12.5.2.5.2.3.3
Subsequence – MCASP DIT-/TDM -Modes Transmit Error Handling
12.5.2.5.2.3.4
Subsequence – MCASP Receive Error Handling
12.6
Camera Peripherals
12.6.1
Camera Serial Interface Receiver (CSI_RX_IF)
12.6.1.1
CSI_RX_IF Overview
12.6.1.1.1
CSI_RX_IF Features
12.6.1.1.2
Unsupported Features
2772
12.6.1.2
CSI_RX_IF Environment
12.6.1.3
Integration
12.6.1.4
CSI_RX_IF Functional Description
12.6.1.4.1
CSI_RX_IF Block Diagram
12.6.1.4.2
CSI_RX_IF Hardware and Software Reset
12.6.1.4.3
CSI_RX_IF Clock Configuration
12.6.1.4.4
CSI_RX_IF Interrupt Events
12.6.1.4.5
CSI_RX_IF Data Memory Organization Details
12.6.1.4.6
CSI_RX_IF PSI_L (DMA) Interface
12.6.1.4.6.1
PSI_L DMA framing
12.6.1.4.6.2
PSI_L DMA error handling due to FIFO overflow
12.6.1.4.7
CSI_RX_IF ECC Protection Support
12.6.1.4.8
CSI_RX_IF Programming Guide
12.6.1.4.8.1
Overview
12.6.1.4.8.2
Controller Configuration
12.6.1.4.8.3
Power on Configuration
12.6.1.4.8.4
Stream Start and Stop
12.6.1.4.8.5
Error Control With Soft Resets
12.6.1.4.8.6
Stream Error Detected – No Error Bypass Mode
12.6.1.4.8.7
Stream Error Detected – Error Bypass Mode
12.6.1.4.8.8
Stream Error Detected – Soft Reset Recovery
12.6.1.4.8.9
Stream Monitor Configuration
12.6.1.4.8.10
Stream Monitor Frame Capture Control
12.6.1.4.8.11
Stream Monitor Timer interrupt
12.6.1.4.8.12
Stream Monitor Line/Byte Counters Interrupt
12.6.1.4.8.13
Example Controller Programming Sequence (Single Stream Operation)
12.6.1.4.8.14
CSI_RX_IF Programming Restrictions
12.6.1.4.8.15
CSI_RX_IF Real-time operating requirements
12.6.2
MIPI D-PHY Receiver (DPHY_RX)
12.6.2.1
DPHY_RX Overview
12.6.2.1.1
DPHY_RX Features
12.6.2.1.2
Unsupported Features
2805
12.6.2.2
DPHY_RX Environment
12.6.2.3
Integration
12.6.2.4
DPHY_RX Functional Description
12.6.2.4.1
DPHY_RX Programming Guide
12.6.2.4.1.1
Overview
12.6.2.4.1.2
Initial Configuration Programming
12.6.2.4.1.2.1
Start-up Sequence Timing Diagram
12.6.2.4.1.3
Common Configuration
12.6.2.4.1.4
Lane Configuration
12.6.3
MIPI D-PHY Transmitter (DPHY_TX)
12.6.3.1
DPHY_TX Subsystem Overview
12.6.3.1.1
DPHY_TX Features
12.6.3.1.2
Unsupported Features
2819
12.6.3.2
Integration
12.6.4
Camera Streaming Interface Transmitter (CSI_TX_IF)
12.6.4.1
CSI_TX_IF Overview
12.6.4.1.1
CSI_TX_IF Ports
12.6.4.2
CSI_TX_IF Features
12.6.4.2.1
CSI_TX_IF Legacy Compatibility
12.6.4.3
CSI_TX_IF Environment
12.6.4.4
CSI_TX_IF Functional Description
12.6.4.4.1
CSI_TX_IF Block Diagram
12.6.4.4.2
CSI_TX_IF Hardware and Software Reset
12.6.4.4.3
CSI_TX_IF Clock Configuration
12.6.4.4.4
CSI_TX_IF Interrupt Events
12.6.4.4.5
CSI_TX_IF Data Memory Organization Details
12.6.4.4.6
CSI_TX_IF PSI_L (DMA) Interface
12.6.4.4.7
CSI_TX_IF ECC Protection Support
12.6.4.5
CSI_TX_IF Programming Guide
12.6.4.5.1
CSI_TX_IF Programming (Configuration Mode)
12.6.4.5.2
CSI_TX_IF System Initialization Programming
12.6.4.5.3
CSI_TX_IF Lane Control Programming
12.6.4.5.4
CSI_TX_IF Virtual Channel and Data Type Management
12.6.4.5.4.1
CSI_TX_IF Data Type Interleaving
12.6.4.5.4.2
CSI_TX_IF Data Type Interleaving with Multiple Interfaces
12.6.4.5.4.3
CSI_TX_IF Virtual Channel Interleaving
12.6.4.5.4.4
CSI_TX_IF Virtual Channel and Data Type Interleaving
12.6.4.5.5
CSI_TX_IF Line Control
12.6.4.5.5.1
CSI_TX_IF Line Control Arbitration
12.6.4.5.6
CSI_TX_IF Lane Manager FSM
12.6.4.5.7
CSI_TX_IF Data Lane Control FSM
12.6.4.5.8
CSI_TX_IF Application Examples
12.6.4.5.8.1
CSI_TX_IF D-PHY Control and Configuration
12.6.4.5.8.2
CSI_TX_IF Clock and Data Lane Enable
12.6.4.5.8.3
CSI_TX_IF DP/DN Signal Swap
12.6.4.5.9
CSI_TX_IF DPHY_TX Status
12.6.4.5.10
CSI_TX_IF ULPS Operation
12.6.4.5.11
CSI_TX_IF System Frame Rate Measurement
12.6.4.5.12
CSI_TX_IF Configuration for PSI_L
12.6.4.5.13
CSI_TX_IF Configuration for Color Bar
12.6.4.5.14
CSI_TX_IF Error Recovery
12.6.4.5.15
CSI_TX_IF Power up/down Sequence
12.7
Timer Modules
12.7.1
Global Timebase Counter (GTC)
12.7.1.1
Global Timebase Counter (GTC)
12.7.1.1.1
GTC Overview
12.7.1.1.1.1
GTC Features
12.7.1.1.1.2
Unsupported Features
2865
12.7.1.2
GTC Functional Description
12.7.1.2.1
GTC Block Diagram
12.7.1.2.2
GTC Counter
12.7.1.2.2.1
Steps to Clear the Counter Value to Zero
12.7.1.2.3
GTC Register Partitioning
12.7.2
RTI-Windowed Watchdog Timer (WWDT)
12.7.2.1
RTI Features
12.7.2.2
Unsupported Features
2874
12.7.2.3
RTI Functional Description
12.7.2.3.1
RTI Digital Windowed Watchdog
12.7.2.3.1.1
RTI Debug Mode Behavior
12.7.2.3.1.2
RTI Low Power Mode Operation
12.7.2.3.2
RTI Digital Watchdog
12.7.2.3.3
RTI Counter Operation
12.7.3
Real-Time Clock (RTC)
12.7.3.1
RTC Overview
12.7.3.1.1
RTC Features
12.7.3.1.2
Unsupported Features
2885
12.7.3.2
RTC Integration
12.7.3.3
RTC Functional Description
12.7.3.3.1
RTC Block Diagram
12.7.3.3.1.1
DIG_CORE uARCH
12.7.3.3.1.2
DIG_ON uARCH
12.7.3.3.1.3
ISO_LVL uARCH
12.7.3.3.1.4
DIG_CORE to DIG_ON updates uARCH
12.7.3.3.2
CPU Interrupt Support
12.7.3.3.2.1
CPU Interrupts
12.7.3.3.3
Programming Usage Guide
12.7.3.3.3.1
No Analog Support
12.7.3.3.3.2
With Analog Support
12.7.3.3.3.2.1
MMR Spurious WRT Protection
12.7.3.3.3.2.2
Crystal Compensation
12.7.3.3.4
Scratch Registers
12.7.3.3.5
KS3 Clock Stop Protocol
12.7.4
Timers
12.7.4.1
Timers Overview
12.7.4.1.1
Timers Features
12.7.4.1.2
Unsupported Features
2906
12.7.4.2
Timers Environment
12.7.4.2.1
Timer External System Interface
12.7.4.3
Integration
12.7.4.4
Timers Functional Description
12.7.4.4.1
Timer Block Diagram
12.7.4.4.2
Timer Power Management
12.7.4.4.2.1
Wake-Up Capability
12.7.4.4.3
Timer Software Reset
12.7.4.4.4
Timer Interrupts
12.7.4.4.5
Timer Mode Functionality
12.7.4.4.5.1
1-ms Tick Generation
12.7.4.4.6
Timer Capture Mode Functionality
12.7.4.4.7
Timer Compare Mode Functionality
12.7.4.4.8
Timer Prescaler Functionality
12.7.4.4.9
Timer Pulse-Width Modulation
12.7.4.4.10
Timer Counting Rate
12.7.4.4.11
Timer Under Emulation
12.7.4.4.12
Accessing Timer Registers
12.7.4.4.12.1
Writing to Timer Registers
12.7.4.4.12.1.1
Write Posting Synchronization Mode
12.7.4.4.12.1.2
Write Nonposting Synchronization Mode
12.7.4.4.12.2
Reading From Timer Counter Registers
12.7.4.4.12.2.1
Read Posted
12.7.4.4.12.2.2
Read Non-Posted
12.7.4.4.13
Timer Posted Mode Selection
12.7.4.5
Timers Low-Level Programming Models
12.7.4.5.1
Timer Global Initialization
12.7.4.5.1.1
Main Sequence – Timer Module Global Initialization
12.7.4.5.2
Timer Operational Mode Configuration
12.7.4.5.2.1
Timer Mode
12.7.4.5.2.1.1
Main Sequence – Timer Mode Configuration
12.7.4.5.2.2
Timer Compare Mode
12.7.4.5.2.2.1
Main Sequence – Timer Compare Mode Configuration
12.7.4.5.2.3
Timer Capture Mode
12.7.4.5.2.3.1
Main Sequence – Timer Capture Mode Configuration
12.7.4.5.2.3.2
Subsequence – Initialize Capture Mode
12.7.4.5.2.3.3
Subsequence – Detect Event
12.7.4.5.2.4
Timer PWM Mode
12.7.4.5.2.4.1
Main Sequence – Timer PWM Mode Configuration
12.8
Internal Diagnostics Modules
12.8.1
Dual Clock Comparator (DCC)
12.8.1.1
DCC Overview
12.8.1.1.1
DCC Features
12.8.1.1.2
Unsupported Features
2951
12.8.1.2
DCC Functional Description
12.8.1.2.1
DCC Counter Operation
12.8.1.2.2
DCC Low Power Mode Operation
12.8.1.2.3
DCC Suspend Mode Behavior
12.8.1.2.4
DCC Single-Shot Mode
12.8.1.2.5
DCC Continuous mode
12.8.1.2.5.1
DCC Continue on Error
12.8.1.2.5.2
DCC Error Count
12.8.1.2.6
DCC Control and count hand-off across clock domains
12.8.1.2.7
DCC Error Trajectory record
12.8.1.2.7.1
DCC FIFO capturing for Errors
12.8.1.2.7.2
DCC FIFO in continuous capture mode
12.8.1.2.7.3
DCC FIFO Details
12.8.1.2.7.4
DCC FIFO Debug mode behavior
12.8.1.2.8
DCC Count read registers
12.8.2
Error Signaling Module (ESM)
12.8.2.1
ESM Overview
12.8.2.1.1
ESM Features
12.8.2.1.2
Unsupported Features
2971
12.8.2.2
ESM Environment
12.8.2.3
Integration
12.8.2.4
ESM Functional Description
12.8.2.4.1
ESM Interrupt Requests
12.8.2.4.1.1
ESM Configuration Error Interrupt
12.8.2.4.1.2
ESM Low Priority Error Interrupt
12.8.2.4.1.2.1
ESM Low Priority Error Level Event
12.8.2.4.1.2.2
ESM Low Priority Error Pulse Event
12.8.2.4.1.3
ESM High Priority Error Interrupt
12.8.2.4.1.3.1
ESM High Priority Error Level Event
12.8.2.4.1.3.2
ESM High Priority Error Pulse Event
12.8.2.4.2
ESM Error Event Inputs
12.8.2.4.3
ESM Error Pin Output
12.8.2.4.4
PWM Mode
12.8.2.4.5
ESM Minimum Time Interval
12.8.2.4.6
ESM Protection for Registers
12.8.2.4.7
ESM Clock Stop
12.8.3
Memory Cyclic Redundancy Check (MCRC) Controller
12.8.3.1
MCRC Overview
12.8.3.1.1
MCRC Features
12.8.3.1.2
Unsupported Features
2993
12.8.3.2
MCRC Functional Description
12.8.3.2.1
MCRC Block Diagram
12.8.3.2.2
MCRC General Operation
12.8.3.2.3
MCRC Modes of Operation
12.8.3.2.3.1
AUTO Mode
12.8.3.2.3.2
Semi-CPU Mode
12.8.3.2.3.3
Full-CPU Mode
12.8.3.2.4
PSA Signature Register
12.8.3.2.5
PSA Sector Signature Register
12.8.3.2.6
CRC Value Register
12.8.3.2.7
Raw Data Register
12.8.3.2.8
Example DMA Controller Setup
12.8.3.2.8.1
AUTO Mode Using Hardware Timer Trigger
12.8.3.2.8.2
AUTO Mode Using Software Trigger
12.8.3.2.8.3
Semi-CPU Mode Using Hardware Timer Trigger
12.8.3.2.9
Pattern Count Register
12.8.3.2.10
Sector Count Register/Current Sector Register
12.8.3.2.11
Interrupts
12.8.3.2.11.1
Overrun Interrupt
12.8.3.2.11.2
Timeout Interrupt
12.8.3.2.11.3
Underrun Interrupt
12.8.3.2.11.4
Compression Complete Interrupt
12.8.3.2.11.5
Interrupt Offset Register
12.8.3.2.11.6
Error Handling
12.8.3.2.12
Power Down Mode
12.8.3.2.13
Emulation
12.8.3.3
MCRC Programming Examples
12.8.3.3.1
Example: Auto Mode Using Time Based Event Triggering
12.8.3.3.1.1
DMA Setup
12.8.3.3.1.2
Timer Setup
12.8.3.3.1.3
CRC Setup
12.8.3.3.2
Example: Auto Mode Without Using Time Based Triggering
12.8.3.3.2.1
DMA Setup
12.8.3.3.2.2
CRC Setup
12.8.3.3.3
Example: Semi-CPU Mode
12.8.3.3.3.1
DMA Setup
12.8.3.3.3.2
Timer Setup
12.8.3.3.3.3
CRC Setup
12.8.3.3.4
Example: Full-CPU Mode
12.8.3.3.4.1
CRC Setup
12.8.4
ECC Aggregator
12.8.4.1
ECC Aggregator Overview
12.8.4.1.1
ECC Aggregator Features
12.8.4.1.2
Unsupported Features
3038
12.8.4.2
Integration
12.8.4.3
ECC Aggregator Functional Description
12.8.4.3.1
ECC Aggregator Block Diagram
12.8.4.3.2
ECC Aggregator Register Groups
12.8.4.3.3
Read Access to the ECC Control and Status Registers
12.8.4.3.4
Serial Write Operation
12.8.4.3.5
Interrupts
12.8.4.3.6
Inject Only Mode
12.8.4.4
ECC Aggregator Configurations
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
12.8.5
Interconnect ECC Aggregators
3080
3081
3082
3083
3084
3085
12.9
Display Subsystem and Peripherals
12.9.1
Display Subsystem (DSS)
12.9.1.1
DSS Overview
12.9.1.1.1
DSS Features
3090
12.9.1.1.2
Unsupported Features
12.9.1.2
DSS Environment
12.9.1.2.1
DSS Parallel Interface
12.9.1.2.1.1
Pixel Data Formats
12.9.1.2.1.2
Display Timing Diagrams
12.9.1.2.2
DSS LVDS Interface
12.9.1.3
Integration
12.9.1.4
DSS Functional Description
12.9.1.4.1
DISPC Functional Description
12.9.1.4.1.1
DISPC Overview
12.9.1.4.1.2
DISPC Clocks
12.9.1.4.1.3
DISPC Resets
12.9.1.4.1.4
DISPC Power Management
12.9.1.4.1.5
DISPC Interrupt Requests
12.9.1.4.1.6
DISPC DMA Engine
12.9.1.4.1.6.1
DISPC DMA Addressing and Bursts
12.9.1.4.1.6.2
DISPC Read DMA Buffers
12.9.1.4.1.6.3
DISPC Flip/Mirror Support
12.9.1.4.1.6.4
DISPC DMA Predecimation
12.9.1.4.1.6.5
DISPC DMA MFLAG Mechanism
12.9.1.4.1.6.6
DISPC DMA Priority Requests Control
12.9.1.4.1.6.7
DISPC DMA Arbitration
12.9.1.4.1.6.8
DISPC DMA Power Modes
12.9.1.4.1.6.8.1
DISPC DMA Low Power Mode
12.9.1.4.1.6.8.2
DISPC DMA Ultra-Low Power Mode
12.9.1.4.1.7
DISPC Pixel Data Formats
12.9.1.4.1.8
DISPC Video Pipelines
12.9.1.4.1.8.1
DISPC VID Replication Logic
12.9.1.4.1.8.2
DISPC VID VC-1 Range Mapping Unit
12.9.1.4.1.8.3
DISPC VID Color Look-Up Table (CLUT)
12.9.1.4.1.8.4
DISPC VID Chrominance Resampling
12.9.1.4.1.8.4.1
Chrominance Resampling for VID Pipeline
12.9.1.4.1.8.4.2
Chrominance Resampling for VIDL1 Pipeline
12.9.1.4.1.8.5
DISPC VID Scaler Unit
12.9.1.4.1.8.6
DISPC VID Color Space Conversion YUV to RGB
12.9.1.4.1.8.7
DISPC VID Brightness/Contrast/Saturation/Hue Control
12.9.1.4.1.8.8
DISPC VID Luma Key Support
12.9.1.4.1.9
DISPC Overlay Managers
12.9.1.4.1.9.1
DISPC Overlay Input Selector
12.9.1.4.1.9.2
DISPC Overlay Mechanism
12.9.1.4.1.9.2.1
Overlay Alpha Blender
12.9.1.4.1.9.2.2
Overlay Transparency Color Keys
12.9.1.4.1.9.3
Overlay 3D Support
12.9.1.4.1.9.4
Overlay Color Bar Insertion
12.9.1.4.1.10
DISPC Video Port Outputs
12.9.1.4.1.10.1
DISPC VP Gamma Correction Unit
12.9.1.4.1.10.2
DISPC VP Color Phase Rotation Unit
12.9.1.4.1.10.3
DISPC VP Color Space Conversion - RGB to YUV
12.9.1.4.1.10.4
DISPC VP BT.656 and BT.1120 Modes
12.9.1.4.1.10.4.1
DISPC BT Mode Blanking
12.9.1.4.1.10.4.2
DISPC BT Mode EAV and SAV
12.9.1.4.1.10.5
DISPC VP Spatial/Temporal Dithering
12.9.1.4.1.10.6
DISPC VP Multiple Cycle Output Format (TDM)
12.9.1.4.1.10.7
DISPC VP Timing Generator and Display Panel Settings
12.9.1.4.1.11
DISPC Safety Features
12.9.1.4.1.11.1
Safety Check Regions
12.9.1.4.1.11.2
Safety Signature Generator Using MISR
12.9.1.4.1.11.3
Safety Checks
12.9.1.4.1.11.4
Safety Check Limitations
12.9.1.4.1.12
DISPC Security Management
12.9.1.4.1.12.1
Security Implementation
12.9.1.4.1.12.2
Secure Mode Configuration
12.9.1.4.1.13
DISPC Shadow Registers
12.9.1.4.2
OLDITX Functional Description
12.9.1.4.2.1
OLDITX Overview
12.9.1.4.2.2
OLDITX Clocks
12.9.1.4.2.3
OLDITX Resets
12.9.1.4.2.4
OLDITX Input Interface
12.9.1.4.2.4.1
OLDITX 24-bit RGB Input
12.9.1.4.2.4.2
OLDITX 18-bit RGB Input
12.9.1.4.2.5
OLDITX Output Mode Configuration
12.9.1.4.2.6
OLDITX Loopback Test Mode
12.9.2
MIPI Display Serial Interface (DSI) Controller
12.9.2.1
DSI Block Diagram
12.9.2.2
DSI Clocking
12.9.2.3
DSI Reset
12.9.2.4
DSI Power Management
12.9.2.5
DSI Interrupts
12.9.2.6
DSI Internal Interfaces
12.9.2.6.1
Video Input Interfaces
12.9.2.6.1.1
Pixel Mapping
12.9.2.6.2
DPI (Pixel Stream Interface)
12.9.2.6.2.1
Signals
12.9.2.6.3
SDI (Serial Data Interface)
12.9.2.6.3.1
Secure Display Support
12.9.2.7
DSI Programming Guide
12.9.2.7.1
Application Guidelines
12.9.2.7.1.1
Overview of a Display Subsystem
12.9.2.7.1.2
D-PHY And DSI Configuration
12.9.2.7.1.3
DSI Controller Initialization
12.9.2.7.1.4
Panel Configuration Using Command Mode
12.9.2.7.1.5
VIDEO Interface Configuration
12.9.2.7.2
Application Considerations
12.9.2.7.2.1
D-PHY Timings Control
12.9.2.7.2.2
Control Block
12.9.2.7.2.3
Video Coherency
12.9.2.7.3
Start-up Procedure
12.9.2.7.4
Interrupt Management
12.9.2.7.4.1
Error and Status Registers
12.9.2.7.4.2
Interrupt Management for Direct Command Registers
12.9.2.7.5
Direct Command Usage
12.9.2.7.5.1
Trigger Mapping Information
12.9.2.7.5.2
Command Mode Settings
12.9.2.7.5.3
Bus Turnaround Sequence
12.9.2.7.5.4
Tearing Effect Control
12.9.2.7.5.5
Tearing Effect Control on Panels with Frame Buffer
12.9.2.7.5.6
Return Path Operation
12.9.2.7.5.7
EoT Packet Management
12.9.2.7.5.8
ECC Correction
12.9.2.7.5.9
LP Transmission and BTA
12.9.2.7.6
Low-power Management
12.9.2.7.7
Video Mode Settings
12.9.2.7.7.1
Video Stream Presentation
12.9.2.7.7.2
Video Stream Settings (VSG)
12.9.2.7.7.3
VCA Configuration
12.9.2.7.7.4
TVG Configuration
12.9.2.7.8
DPI To DSI Programming
12.9.2.7.8.1
DSI and DPHY Operation
12.9.2.7.8.2
Pixel Clock to TX_BYTE_CLK Variation
12.9.2.7.8.3
LP Operation
12.9.2.7.8.4
DPI Interface Burst Operation
12.9.2.7.9
Programming the DSITX Controller to Match the Incoming DPI Stream
12.9.2.7.9.1
Vertical Timing
12.9.2.7.9.2
Horizontal Timing for Non-Burst Mode with Sync Pulses
12.9.2.7.9.3
Event Mode Horizontal Timing
12.9.2.7.9.4
Burst Event Mode Horizontal Timing
12.9.2.7.9.5
Burst Mode Operation
12.9.2.7.9.6
Example Configurations
12.9.2.7.9.7
Stereoscopic Video Support
12.9.2.7.10
DSITX Video Stream Variable Refresh
13
On-Chip Debug
13.1
On-Chip Debug Overview
13.2
On-Chip Debug Features
3224
13.3
On-Chip Debug Functional Description
13.3.1
On-Chip Debug Block Diagram
13.3.2
Device Interfaces
13.3.2.1
JTAG Interface
13.3.2.2
Trigger and Debug Boot Mode Interface
13.3.2.3
Trace Port Interface
13.3.3
Debug and Boundary Scan Access and Control
13.3.4
Debug Boot Modes and Boundary Scan Compliance
13.3.5
Power, Reset, Clock Management
13.3.6
Debug Cross Triggering
13.3.7
WKUP_R5F Debug
13.3.8
A53SS0 Debug
13.3.9
SoC Debug and Trace
13.3.9.1
Software messaging trace
13.3.9.2
Debug-Aware Peripherals
13.3.9.3
Traffic Monitoring With Bus Probes
13.3.9.4
Global timestamping for trace
13.3.10
Trace Traffic
13.3.10.1
Trace Sources
13.3.10.2
Trace Infrasctructure
13.3.10.3
Trace Sinks
13.3.11
Application Support
14
Revision History
12.4
Industrial and Communication Interfaces