SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
This device supports an Arm® CoreSight™ compliant four-channel programmable on-chip Cross Triggering network. In addition to the four-channel on-chip network, this device implements two channels of product level triggering via the EMU0 and EMU1 device pins.
Conceptually, each channel of Cross Triggering can be viewed as mapping of a user-defined set of events to a user-defined set of actions, where the occurrence of any event in the set-of-events results in the generation of the set-of-actions. Table 13-7 provides a domain-level summary of the supported events and actions.
Domain | Events | Actions |
---|---|---|
Product-Level | Zero detected on EMU0 input pin | EMU0 output pin driven to Zero |
Zero detected on EMU1 input pin | EMU1 output pin driven to Zero | |
SoC Debug | TBR Acquisition Complete | TPIU insert trigger packet |
TBR Embedded buffer is full | TPIU start flush process | |
System reset asserted | TBR insert trigger packet | |
Bus Probe-n match | TBR start flush process | |
STM write to a TRIG location | Bus Probe-n Start | |
STM write to a trigger-enabled stimulus port | Bus Probe-n Stop | |
has halted | – halt request | |
PMU generated interrupt | – resume request | |
ETM External Out (EXTOUT) trigger | ETM External In (EXTIN) trigger | |
A53SS0 | A53SS0 core-n has halted | A53SS0 core-n – halt request |
PMU generated interrupt | A53SS0 core-n – resume request | |
ETM trigger | CTI interrupt | |
-- | ETM External In (EXTIN) trigger |