SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The controller transmit-only mode prevents the processor from reading the MCSPI_RXi register (minimizing data movement) when only transmission is meaningful.
The controller transmit-only mode is programmable per channel (the MCSPI_CHiCONF[13-12] TRM bit field). Transmission starts only after data is loaded into the MCSPI_TXi register.
Rule 1 and Rule 2, defined in Section 12.1.3.4.3.2, apply in this mode.
Rule 3, defined in Section 12.1.3.4.3.2, does not apply.
In controller transmit-only mode, the MCSPI_RXi register state FULL does not prevent transmission and the MCSPI_RXi register is always overwritten with the new MCSPI word. This event is not significant when only transmission is meaningful. Thus, the RX0_OVERFLOW bit in the MCSPI_IRQSTATUS register is never set in this mode.
The hardware automatically disables the RX_FULL interrupt and the DMA read requests.
The transfer status is given by the MCSPI_CHiSTAT[2] EOT bit.