SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The input to the OLDITX is a standard DPI interface bus (direct output of a DSS DISPC video port), which consists of the following signals:
OLDITX receives 18-bit or 24-bit RGB input source data from the DSS DISPC video port. The DSS interface is clocked on the rising edge of OLDI_FWD_P_CLK pixel clock (whose frequency is exactly 1/7 of the OLDI_PLL_CLK serial clock). The DATA, VS, HS, and DE signals are treated as data to be mapped onto the LVDS output shifter. The start of accepting and processing the DSS interface data happens after DSS0_VP_DSS_OLDI_CFG[0] ENABLE bit is asserted to 0x1 and synchronized to the internal pixel clock.