The McASP module supports the
following features:
- Transmit control section consisting of:
- Transmit state machine supporting IIS and DIT modes
- Transmit formatter supporting IIS and DIT options
- Transmit clock generation with auto-switch on bad clock detect
- Transmit frame sync generation
- Transmit TDM control
- Receive control section consisting of:
- Receive state machine implementing supported protocols
- Receive clock generation
- Receive frame sync generation
- Receive TDM control
- Option to synchronize to transmit control section
- Multiple shift registers (2 to 16 specified at module generation):
- Individual transmit / receive / off selection
- Transmit in IIS or DIT mode
- Flexible order in memory to ease DMA operation versus pinout
- TDM mode function selection (Z, 0, 1)
- Single RX interrupt generation, with individual enables for:
- Data Ready: all slots, last slot
- Error: overrun, unexpected frame sync, bad clock
- Two DMA events (RX, TX)
- Slot counter exported with DMA request to enable per-slot DMA request (or
left/right, at minimum)
- Automatic mute output pin option with programmable polarity on error
detect