SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The A53 CPU recieves interrupts at its inputs (IRQ, FIQ, VIRQ, VFIQ) via the dedicated Arm GIC-500 Interrupt Controller, which resides at the SoC level (MAIN Domain) and is integrated inside the GIC0 Subsystem. The GIC-500 supports all four A53 cores in the system.
The GIC-500 is compliant to the Arm GICv3 standard and supports four types of interrupts:
The mapping of PPIs and SPIs to the GIC-500 interrupt inputs can be found in Interrupts.
For a brief list of features supported by the GIC-500 module, see the Interrupts chapter.
For detailed description of the GIC-500 module, see the Arm® CoreLink™ GIC-500 Generic Interrupt Controller Technical Reference Manual.