SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Figure 12-407 shows the RTI module counter blocks. The RTI module supports two counter blocks.
Each block consists of two 32 bit up counters - Up Counter (UC) and Free Running Counter (FRC). The Up Counter (RTI_RTICAUC0 or RTI_RTICAUC1 register) is driven by the RTI_FCLK and counts up until the compare value in the Compare Up Counter register (RTI_RTICPUC0 or RTI_RTICPUC1) is reached. When the compare matches, the second counter (RTI_RTICAFRC0 or RTI_RTICAFRC1 register), which is a free running counter, is incremented. At the same time UCx is reset to zero.
To ensure the consistency of the counters, when both counter value have to be determined, the Free Running Counter has to be read first. This will ensure that at the CPU read cycle, the Up Counter value is stored in the counter register. The second read is done on the Up Counter register, which holds then the value of the counter cycle of the previous read on the Free Running Counter register.
Both blocks provide also a capture feature on external events. Two capture sources can trigger the capture event. Which event triggers block 0 or block 1 is configurable from the RTI_RTICAPCTRL register. The sources are coming from the interrupt manager, in order to be able to generate a capture event when one of the peripheral modules has generated an interrupt. The peripheral, which can generate an event is configured in the interrupt manager. When the event is detected, UCx and FRCx are stored in Capture Up Counter (RTI_RTICAUC0 or RTI_RTICAUC1) and Capture Free Running Counter (RTI_RTICAFRC0 or RTI_RTICAFRC1) registers. The read order of the captured values has to be like the order of the actual counters. So the CAFRCx has to be read first and the CAUCx registers has to be read after the CAFRCx value was determined. While the CAFRCx is read the CAUCx value is loaded into a shadow register to ensure data consistency, if during the two reads of the captured data another capture event happens. If the application fails to read the two registers before a second capture event happens, the previous data will be overwritten.
Figure 12-408 shows the block diagram for one compare block. The RTI module supports four compare blocks.
In order to generate interrupt requests to the interrupt manager, there are four compare registers (RTI_RTICOMP0, RTI_RTICOMP1, RTI_RTICOMP2, and RTI_RTICOMP3). Each of the compare registers can be configured to work either on FRC0 (Counter block0) or FRC1 (Counter block1). When the counter value matches the compare value, an interrupt is generated. This sets an interrupt request line to the interrupt manager. The compare value gets updated automatically with the value stored in Update Compare (RTI_RTIUDCP0, RTI_RTIUDCP1, RTI_RTIUDCP2, and RTI_RTIUDCP3) registers when the compare matches. This gives the ability to generate periodic interrupts/DMA requests without having to update the compare value by software.
An optional feature allows an application to program another compare value which is then used to clear the interrupt request line. This feature is supported by four compare clear registers (RTI_RTICOMP0CLR, RTI_RTICOMP1CLR, RTI_RTICOMP2CLR, and RTI_RTICOMP3CLR). When the counter value matches the compare clear value, the interrupt line is cleared. This clears the interrupt request line to the interrupt manager. The compare clear value gets updated automatically with the value stored in Update Compare (RTI_RTIUDCPx) registers when the compare matches.