The R5FSS supports the following features:
- Single-core Arm Cortex-R5F
- Core revision: r1p3
- Armv7-R profile
- L1 memory system
- 32KB instruction
cache
- 4x8KB
ways
- SECDED
ECC protected per 64 bits
- 32KB data cache
- 4x8KB
ways
- SECDED
ECC protected per 32 bits
- 64KB
tightly-coupled memory (TCM)
- SECDED
ECC protected per 32 bits
- TCM hard
error cache Implemented in CPU
- Readable/writable from system
- TCMs
initialized (to 0's) at reset
- Split
into A and B banks (with B further splitting into B0 and
B1 interleaved banks)
- 32KB TCMA (ATCM)
- 16KB TCMB0 (B0TCM)
- 16KB TCMB1 (B1TCM)
- Low interrupt latency
with restartable instructions
- Non-maskable interrupt
(NMI)
- Full-precision floating
point (VFPv3)
- 16 region memory
protection unit (MPU)
- 8 breakpoints
- 8 watchpoints
- Dynamic branch prediction
with global history buffer and 4-entry return stack
- CoreSight debug access
port (DAP)
- CoreSight embedded trace
macrocell (ETM-R5) interface
- Performance monitoring
unit (PMU)
- Interfaces
- 64-bit VBUSM initiator pair (1
read, 1 write) for L3 memory accesses
- 64-bit VBUSM target for TCM
access
- Also allows
access to cache for debug purposes
- 32-bit VBUSP initiator for
peripheral access
- 32-bit VBUSP target
configuration port
- 32-bit VBUSP target debug port
- Allows access to
all R5FSS internal debug logic
- Synchronous clock domain crossing on all interfaces
- Interfaces can run at an integer multiple of the core frequency
- 32-bit to 36-bit region-based address translation
(RAT) on memory access initiators
- 4 regions
- Base address +
size
- Must be size
aligned
- Integrated vectored interrupt manager (VIM)
- 256 interrupts
- Each interrupt
programmable as either IRQ or FIQ
- Each interrupt
has a programmable enable mask
- Each interrupt
has a programmable 4-bit priority
- Priority interrupt supported
- Vectored interrupt interface
- Compatible with R5F VIC port
- Programmable 32-bit vector address per interrupt
- Address is SECDED error protected
- Default vector addresses provided on DED
- Software interrupt generation
- Integrated ECC aggregators
- Support for error injection to all supported ECC memory blocks to test ECC functionality (add-on function from TI)
- One ECC aggregator to cover all
RAMs and caches
- Standard Arm CoreSight debug and trace architecture at the R5FSS level
- Cross triggering: Supported by cross trigger interface (CTI) (per CPU) and cross trigger matrix (CTM) components
- Processor trace: Supported by embedded trace macrocell (ETM) (per CPU) and advanced trace bus (ATB) funnel components
- Boot
See Section 7.3.2 for a functional block diagram and more details on the R5FSS.