ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.
PCI register offset: | 1Bh | |
Register type: | Read/Write | |
Default value: | 00h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |