ZHCSS37J 数据表 | 德州仪器 TI.com.cn

ZHCSS37J may 2009 – january 2021 XIO2001

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PNP|128
- MPQF060E
ZWS|169
- MPBGAK4B
ZAJ|144
- MPBG878A

散热焊盘机械数据 (封装 | 引脚)

PNP|128
- PPTD154D

订购信息

6.7 PCI Express Differential Receiver Input Ranges

PARAMETER	TERMINALS	MIN	MAX	UNIT	COMMENTS
UI⁽¹⁾ Unit interval	RXP, RXN	399.88	400.12	ps	Each UI is 400 ps ±300 ppm. UI does not account for SSC dictated variations.
V_{RX-DIFF-PP-CC}⁽²⁾ Differential input peak-to-peak voltage	RXP, RXN	0.175	1.200	V	V_RX-DIFFp-p = 2*\|V_RXP – V_RXN\|
T_RX-EYE⁽²⁾ ⁽³⁾ Minimum receiver eye width	RXP, RXN	0.4		UI	The maximum interconnect media and transmitter jitter that can be tolerated by the receiver is derived as T_{RX-MAX-JITTER} = 1 – T_RX-EYE = 0.6 UI
T_{RX-EYE-MEDIAN-to-MAX-JITTER}⁽²⁾ ⁽³⁾ Maximum time between the jitter median and maximum deviation from the median	RXP, RXN		0.3	UI	Jitter is defined as the measurement variation of the crossing points (V_RX-DIFFp-p = 0 V) in relation to recovered TX UI. A recovered TX UI is calculated over 3500 consecutive UIs of sample data. Jitter is measured using all edges of the 250 consecutive UIs in the center of the 3500 UIs used for calculating the TX UI.
BW_RX-PLL-HI⁽⁶⁾ Maximum Rx PLL bandwidth	RXP, RXN		22	MHz	Second order PLL jitter transfer bounding function.
BW_{RX-PLL-LO-3DB}⁽⁶⁾ Minimum Rx PLL for 3 dB peaking	RXP, RXN	1.5		MHz	Second order PLL jitter transfer bounding function.
V_RX-CM-AC-P⁽²⁾ AC peak common mode input voltage	RXP, RXN		150	mV	V_RX-CM-AC-P = RMS(\|V_RXP + V_RXN\|/2 – V_RX-CM-DC) V_RX-CM-DC = DC_(avg) of \|V_RXP + V_RXN\|/2.
RL_RX-DIFF⁽⁴⁾ Differential return loss	RXP, RXN	10		dB	Measured over 50 MHz to 1.25 GHz with the P and N lines biased at +300 mV and –300 mV, respectively.
RL_RX-CM⁽⁴⁾ Common mode return loss	RXP, RXN	6		dB	Measured over 50 MHz to 1.25 GHz with the P and N lines biased at +300 mV and –300 mV, respectively.
Z_RX-DIFF-DC⁽⁵⁾ DC differential input impedance	RXP, RXN	80	120	Ω	RX dc differential mode impedance
Z_RX-DC⁽⁴⁾ ⁽⁵⁾ DC input impedance	RXP, RXN	40	60	Ω	Required RXP as well as RXN dc impedance (50 Ω ±20% tolerance).
Z_{RX-HIGH-IMP-DC-POS}⁽⁷⁾ DC input CM input impedance for V > 0 during reset or powerdown	RXP, RXN	50		kΩ	Rx DC CM impedance with the Rx terminations not powered, measured over the range 0 to 200 mV with respect to ground.
Z_{RX-HIGH-IMP-DC-NEG}⁽⁷⁾ DC input CM input impedance for V > 0 during reset or powerdown	RXP, RXN	1		kΩ	Rx DC CM impedance with the Rx terminations not powered, measured over the range 0 to 200 mV with respect to ground.
V_{RX-IDLE-DET-DIFFp-p} Electrical idle detect threshold	RXP, RXN	65	175	mV	V_{RX-IDLE-DET-DIFFp-p} = 2*\|V_RXP – V_RXN\| measured at the receiver package terminals
T_{RX-IDLE-DET-DIFF-ENTER-TIME} Unexpected electrical idle enter detect threshold integration time	RXP, RXN		10	ms	An unexpected electrical idle (V_RX-DIFFp-p < V_{RX-IDLE-DET-DIFFp-p}) must be recognized no longer than T_{RX-IDLE-DET-DIFF-ENTER-TIME} to signal an unexpected idle condition.

(1) No test load is necessarily associated with this value.

(2) Specified at the measurement point and measured over any 250 consecutive UIs. A test load must be used as the RX device when taking measurements. If the clocks to the RX and TX are not derived from the same reference clock, then the TX UI recovered from 3500 consecutive UIs is used as a reference for the eye diagram.

(3) A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive TX UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, then the TX UI recovered from 3500 consecutive UIs must be used as the reference for the eye diagram.

(4) The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV and the N line biased to .300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 . to ground for both the P and N line (i.e., as measured by a Vector Network Analyzer with 50-. probes). The series capacitors CTX is optional for the return loss measurement.

(5) Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCI Express reset to the detect state (the initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on the unconfigured lane of a port.

(6) A single PLL bandwidth and peaking value of 1.5 to 22 MHz and 3 dB are defined.

(7) Z_{RX-HIGH-IMP-DC-NEG} and Z_{RX-HIGH-IMP-DC-POS} are defined respectively for negative and postive voltages at the input of the receiver.