ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
This read-only register indicates to host software what the state of the secondary bus will be when the bridge is placed in D3. See Table 8-30 for a complete description of the register contents.
PCI register offset: | 4Eh | |
Register type: | Read-only | |
Default value: | 40h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION | |
---|---|---|---|---|
7 | BPCC | R | Bus power/clock control enable. This bit indicates to the host software if the bus secondary clocks are stopped when the bridge is placed in D3. The state of the BPCC bit is controlled by bit 11 (BPCC_E) in the general control register (offset D4h, see Section 8.4.66). | |
0 = 1 = | The secondary bus clocks are not stopped in D3 The secondary bus clocks are stopped in D3 | |||
6 | BSTATE | R | B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2. | |
5:0 | RSVD | R | Reserved. Returns 00 0000b when read. |