ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream. See Table 8-16 for a complete description of the register contents.
PCI register offset: | 1Ch | |
Register type: | Read-only, Read/Write | |
Default value: | 01h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
7:4 | IOBASE | RW | I/O base. Defines the bottom address of the I/O address range that determines when to forward I/O transactions from one interface to the other. These bits correspond to address bits [15:12] in the I/O address. The lower 12 bits are assumed to be 000h. The 16 bits corresponding to address bits [31:16] of the I/O address are defined in the I/O base upper 16 bits register (offset 30h, see Section 8.4.25). |
3:0 | IOTYPE | R | I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing. |