ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
The programming model of the memory-mapped TI proprietary register space is unique to this device.
All bits marked with a ☆ are sticky bits and are reset by a global reset ( GRST) or the internally-generated power-on reset. All bits marked with a(1) are reset by a PCI Express reset ( PERST), a GRST or the internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or the internally-generated power-on reset.
REGISTER NAME | OFFSET | |||
---|---|---|---|---|
Reserved | Revision ID | Device control map ID | 000h | |
Reserved | 004h–03Ch | |||
GPIO data(1) | GPIO control (1) | 040h | ||
Serial-bus control and status(1) | Serial-bus slave address(1) | Serial-bus word address(1) | Serial-bus data(1) | 044h |
Serial IRQ edge control(1) | Reserved | Serial IRQ mode control(1) | 048h | |
Reserved | Serial IRQ status(1) | 04Ch | ||
Cache Timer Transfer Limit(1) | PFA Request Limit(1) | 050h | ||
Cache Timer Upper Limit(1) | Cache Timer Lower Limit(1) | 054h | ||
Reserved | 058h–FFFh |