ZHCSS37J
may 2009 – january 2021
XIO2001
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
Pin Assignments
Pin Descriptions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Handling Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information #GUID-4E9F689A-942D-492C-8F28-F3CC5F1BD0E6/SCPS2129637AN1
6.5
Nominal Power Consumption
6.6
PCI Express Differential Transmitter Output Ranges
6.7
PCI Express Differential Receiver Input Ranges
6.8
PCI Express Differential Reference Clock Input Ranges #GUID-60875016-888B-4DD4-A309-543B497BAC9F/SCPS1718455
6.9
PCI Bus Electrical Characteristics
6.10
3.3-V I/O Electrical Characteristics
6.11
PCI Bus Timing Requirements
6.12
Power-Up/-Down Sequencing
6.12.1
Power-Up Sequence
6.12.2
Power-Down Sequence
7
Parameter Measurement Information
25
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Bridge Reset Features
8.3.2
PCI Express Interface
8.3.2.1
2.5-Gb/s Transmit and Receive Links
8.3.2.2
Transmitter Reference Resistor
8.3.2.3
Reference Clock
8.3.2.4
Reset
8.3.2.5
Beacon
8.3.2.6
Wake
8.3.2.7
Initial Flow Control Credits
8.3.2.8
PCI Express Message Transactions
8.3.3
PCI Port Arbitration
8.3.3.1
Classic PCI Arbiter
8.3.4
Configuration Register Translation
8.3.5
PCI Interrupt Conversion to PCI Express Messages
8.3.6
PME Conversion to PCI Express Messages
8.3.7
PCI Express to PCI Bus Lock Conversion
8.3.8
Two-Wire Serial-Bus Interface
8.3.8.1
Serial-Bus Interface Implementation
8.3.8.2
Serial-Bus Interface Protocol
8.3.8.3
Serial-Bus EEPROM Application
8.3.8.4
Accessing Serial-Bus Devices Through Software
8.3.9
Advanced Error Reporting Registers
8.3.10
Data Error Forwarding Capability
8.3.11
General-Purpose I/O Interface
8.3.12
Set Slot Power Limit Functionality
8.3.13
PCI Express and PCI Bus Power Management
8.3.14
Auto Pre-Fetch Agent
8.4
Register Maps
8.4.1
Classic PCI Configuration Space
8.4.2
Vendor ID Register
8.4.3
Device ID Register
8.4.4
Command Register
8.4.5
Status Register
8.4.6
Class Code and Revision ID Register
8.4.7
Cache Line Size Register
8.4.8
Primary Latency Timer Register
8.4.9
Header Type Register
8.4.10
BIST Register
8.4.11
Device Control Base Address Register
8.4.12
Primary Bus Number Register
8.4.13
Secondary Bus Number Register
8.4.14
Subordinate Bus Number Register
8.4.15
Secondary Latency Timer Register
8.4.16
I/O Base Register
8.4.17
I/O Limit Register
8.4.18
Secondary Status Register
8.4.19
Memory Base Register
8.4.20
Memory Limit Register
8.4.21
Prefetchable Memory Base Register
8.4.22
Prefetchable Memory Limit Register
8.4.23
Prefetchable Base Upper 32-Bit Register
8.4.24
Prefetchable Limit Upper 32-Bit Register
8.4.25
I/O Base Upper 16-Bit Register
8.4.26
I/O Limit Upper 16-Bit Register
8.4.27
Capabilities Pointer Register
8.4.28
Interrupt Line Register
8.4.29
Interrupt Pin Register
8.4.30
Bridge Control Register
8.4.31
Capability ID Register
8.4.32
Next Item Pointer Register
8.4.33
Subsystem Vendor ID Register
8.4.34
Subsystem ID Register
8.4.35
Capability ID Register
8.4.36
Next Item Pointer Register
8.4.37
Power Management Capabilities Register
8.4.38
Power Management Control/Status Register
8.4.39
Power Management Bridge Support Extension Register
8.4.40
Power Management Data Register
8.4.41
MSI Capability ID Register
8.4.42
Next Item Pointer Register
8.4.43
MSI Message Control Register
8.4.44
MSI Message Lower Address Register
8.4.45
MSI Message Upper Address Register
8.4.46
MSI Message Data Register
8.4.47
PCI Express Capability ID Register
8.4.48
Next Item Pointer Register
8.4.49
PCI Express Capabilities Register
8.4.50
Device Capabilities Register
8.4.51
Device Control Register
8.4.52
Device Status Register
8.4.53
Link Capabilities Register
8.4.54
Link Control Register
8.4.55
Link Status Register
8.4.56
Serial-Bus Data Register
8.4.57
Serial-Bus Word Address Register
8.4.58
Serial-Bus Slave Address Register
8.4.59
Serial-Bus Control and Status Register
8.4.60
GPIO Control Register
8.4.61
GPIO Data Register
8.4.62
TL Control and Diagnostic Register 0
8.4.63
Control and Diagnostic Register 1
8.4.64
Control and Diagnostic Register 2
8.4.65
Subsystem Access Register
8.4.66
General Control Register
8.4.67
Clock Control Register
8.4.68
Clock Mask Register
8.4.69
Clock Run Status Register
8.4.70
Arbiter Control Register
8.4.71
Arbiter Request Mask Register
8.4.72
Arbiter Time-Out Status Register
8.4.73
Serial IRQ Mode Control Register
8.4.74
Serial IRQ Edge Control Register
8.4.75
Serial IRQ Status Register
8.4.76
Pre-Fetch Agent Request Limits Register
8.4.77
Cache Timer Transfer Limit Register
8.4.78
Cache Timer Lower Limit Register
8.4.79
Cache Timer Upper Limit Register
8.5
PCI Express Extended Configuration Space
8.5.1
Advanced Error Reporting Capability ID Register
8.5.2
Next Capability Offset/Capability Version Register
8.5.3
Uncorrectable Error Status Register
8.5.4
Uncorrectable Error Mask Register
8.5.5
Uncorrectable Error Severity Register
8.5.6
Correctable Error Status Register
8.5.7
Correctable Error Mask Register
8.5.8
Advanced Error Capabilities and Control Register
8.5.9
Header Log Register
8.5.10
Secondary Uncorrectable Error Status Register
8.5.11
Secondary Uncorrectable Error Severity
8.5.12
Secondary Error Capabilities and Control Register
8.5.13
Secondary Header Log Register
8.6
Memory-Mapped TI Proprietary Register Space
8.6.1
Device Control Map ID Register
8.6.2
Revision ID Register
8.6.3
GPIO Control Register
8.6.4
GPIO Data Register
8.6.5
Serial-Bus Data Register
8.6.6
Serial-Bus Word Address Register
8.6.7
Serial-Bus Slave Address Register
8.6.8
Serial-Bus Control and Status Register
8.6.9
Serial IRQ Mode Control Register
8.6.10
Serial IRQ Edge Control Register
8.6.11
Serial IRQ Status Register
8.6.12
Pre-Fetch Agent Request Limits Register
8.6.13
Cache Timer Transfer Limit Register
8.6.14
Cache Timer Lower Limit Register
8.6.15
Cache Timer Upper Limit Register
9
Application, Implementation, and Layout
9.1
Application Information
9.2
Typical Application
9.2.1
In-Card Implementation
9.2.1.1
Design Requirements
9.2.1.1.1
VCCP Clamping Rail
9.2.1.1.2
Combined Power Outputs
9.2.1.1.3
Auxiliary Power
9.2.1.1.4
VSS and VSSA Pins
9.2.1.1.5
Capacitor Selection Recommendations
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
PCI Bus Interface
9.2.1.2.1.1
Bus Parking
9.2.1.2.1.2
I/O Characteristics
9.2.1.2.1.3
Clamping Voltage
9.2.1.2.1.4
PCI Bus Clock Run
9.2.1.2.1.5
PCI Bus External Arbiter
9.2.1.2.1.6
MSI Messages Generated from the Serial IRQ Interface
9.2.1.2.1.7
PCI Bus Clocks
9.2.2
External EEPROM
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.3
JTAG Interface
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.2.4
Combined Power
9.2.4.1
Design Requirements
9.2.4.2
Detailed Design Procedure
9.2.5
Power Filtering
9.2.5.1
Design Requirements
9.2.5.2
Detailed Design Procedure
9.3
Layout
9.3.1
Layout Guidelines
9.3.2
Layout Example
9.4
Power Supply Recommendations
9.4.1
1.5-V and 3.3-V Digital Supplies
9.4.2
1.5-V and 3.3-V Analog Supplies
9.4.3
1.5-V PLL Supply
9.4.4
Power-Up/Down Sequencing
9.4.5
Power Supply Filtering Recommendations
10
Device and Documentation Support
10.1
Documents Conventions
10.1.1
XIO2001 Definition
10.2
Documentation Support
10.2.1
Related Documents
10.2.1.1
接收文档更新通知
10.3
支持资源
10.4
Trademarks
10.5
静电放电警告
10.6
术语表
11
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
PNP|128
MPQF060E
ZWS|169
MPBGAK4B
ZAJ|144
MPBG878A
散热焊盘机械数据 (封装 | 引脚)
PNP|128
PPTD154D
订购信息
zhcss37j_oa
zhcss37j_pm
1
特性
完整的 ×1
PCI Express™
吞吐量
完全符合
PCI Express 至 PCI/PCI-X 桥接器规范
修订版 1.0
完全符合
PCI Express 基础规范
修订版 2.0
完全符合
PCI 本地总线规范
修订版 2.3
PCI Express 高级错误报告功能,包括 ECRC 支持
支持 D1、D2、D3
hot
和 D3
cold
当 PCI Express 链路上的数据包活动处于空闲状态(使用 L0s 和 L1 状态)时,活动状态链路电源管理功能可实现省电
唤醒事件和信标支持
错误转发,包括 PCI Express 数据中毒和 PCI 总线奇偶校验错误
使用 100MHz 差分 PCI Express 通用参考时钟或 125MHz 单端参考时钟
支持可选展频参考时钟
稳健的流水线架构可尽可能降低事务延迟
完整的 PCI 本地总线 66MHz/32 位吞吐量
支持六个从属 PCI 总线主器件,具有可配置的内部 2 级优先级方案
内部 PCI 仲裁器支持多达 6 个外部 PCI 主器件
适用于串行 IRQ 中断的高级 PCI Express 消息信号中断生成功能
外部 PCI 总线仲裁器选项
支持 PCI 总线
LOCK
用于生产测试的 JTAG/BS
支持 PCI-Express
CLKREQ
支持时钟运行和功率覆盖
六个缓冲 PCI 时钟输出(25MHz、33MHz、50MHz 或 66MHz)
PCI 总线接口 3.3V 和 5.0V(在 5.0V 时
仅为 25MHz 或 33MHz)容差选项
仅当主电源关闭时,集成 AUX 电源开关由 V
AUX
电源供电
五个 3.3V 多功能通用 I/O 端子
存储器映射 EEPROM 串行总线控制器,支持插件卡的 PCI Express 功率预算/限制扩展
小尺寸无铅 144 焊球 ZAJ nFBGA、无铅 169 焊球 ZWS nFBGA 和
PowerPad™
HTQFP 128 引脚 PNP 封装