ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 8-52 for a complete description of the register contents.
PCI register offset: | DAh | |
Register type: | Read-only | |
Default value: | 00h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION | |
---|---|---|---|---|
7:1 | RSVD | R | Reserved. Returns 000 0000b when read. | |
0(1) | SEC_CLK_STATUS | RU | Secondary clock status. This bit indicates the status of the PCI bus secondary clock outputs. 0 = Secondary clock running 1 = Secondary clock stopped |