ZHCSS37J may 2009 – january 2021 XIO2001
PRODUCTION DATA
This register controls the behavior of the serial IRQ controller. See Table 8-56 for a complete description of the register contents.
PCI register offset: | E0h | |
Register type: | Read-only, Read/Write | |
Default value: | 00h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION | |
---|---|---|---|---|
7:4 | RSVD | R | Reserved. Returns 0h when read. | |
3:2(1) | START_WIDTH | RW | Start frame pulse width. Sets the width of the start frame for a SERIRQ stream. 00 = 4 clocks (default) 01 = 6 clocks 10 = 8 clocks 11 = Reserved | |
1(1) | POLLMODE | RW | Poll mode. This bit selects between continuous and quiet mode. 0 = Continuous mode (default) 1 = Quiet mode | |
0(1) | DRIVEMODE | RW | RW Drive mode. This bit selects the behavior of the serial IRQ controller during the recovery cycle. 0 = Drive high (default) 1 = 3-state |